RTL Verification Engineer

Vertical Compute SRL; Leuven; Hybrid; EUR 70,000 - 110,000; Full time

Job summary

Vertical Compute is seeking an RTL Verification Engineer to lead verification of our 3D-integrated chiplets, focusing on top-level validation of the chiplets and their tight coupling with the VIM memory technology. You will work with Front-End RTL Design, System Architecture and Software teams to ensure tape-out readiness.

The role requires strong SystemVerilog/UVM expertise, a track record in ASIC/SoC verification, and excellent collaboration and English communication.

Qualifications

• Proven track record in ASIC/SoC functional verification, including top-level verification of complex multi-IP designs or AI compute accelerators.
• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.
• Strong expertise in SystemVerilog, UVM, assertion-based verification, and coverage-driven verification for complex hardware architectures.
• Strong collaborative mindset and problem-solving skills to work effectively with cross-functional FE Design, System, and SW teams.
• Fluency in English with excellent written and verbal communication skills.

Responsibilities

• Lead top-level functional verification for our next-generation AI compute chiplet, ensuring complete protocol compliance and robust multi-die integration.
• Architect, deploy, and maintain advanced UVM/SystemVerilog testbenches, assertions, and constrained-random test plans for memory and compute subsystems.
• Drive coverage-driven verification, target debug, and root-cause analysis across complex hardware-software boundary scenarios.
• Collaborate closely with Front-End RTL Design, System Architecture, and Software/Compiler teams to achieve full tape-out readiness and post-silicon validation.
• Benchmark and analyze system-level performance to demonstrate the throughput, bandwidth, and energy efficiency of Vertical Compute's VIM™ technology.

Skills

ASIC/SoC verification

SystemVerilog

UVM

Constrained-random testing

HW-SW collaboration

Education

Electrical/Computer Engineering or Microelectronics (B.S./M.S./Ph.D.)

Tools

SystemVerilog

UVM

Assertions

Job description

About Us: AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.

Why Now: After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.

About the role:

We are looking for an RTL Verification Engineer to lead and execute the verification of our Vertical Compute's 3D-integrated chiplets. In this role, you will specifically focus on the top-level verification of the chiplets. Coupling high-performance AI accelerators directly with our proprietary Vertical Integrated Memory (VIM™), these chiplets showcase the full capabilities of our technology to address the AI market.

Key Responsibilities:

• Lead top-level functional verification for our next-generation AI compute chiplet, ensuring complete protocol compliance and robust multi-die integration.

• Architect, deploy, and maintain advanced UVM/SystemVerilog testbenches, assertions, and constrained-random test plans for memory and compute subsystems.

• Drive coverage-driven verification, target debug, and root-cause analysis across complex hardware-software boundary scenarios.

• Collaborate closely with Front-End RTL Design, System Architecture, and Software/Compiler teams to achieve full tape-out readiness and post-silicon validation.

• Benchmark and analyze system-level performance to demonstrate the throughput, bandwidth, and energy efficiency of Vertical Compute's VIM™ technology.

About the team:

This role is part of the Hardware Design team within Vertical Compute's Product & System organization, reporting directly to the HW Team Manager. You will work in close collaboration with the Front-End Design and Software teams, partnering across cross-functional engineering groups to ensure the seamless functionality, performance, and successful delivery of our vertical compute products.

About who you are:

• Proven track record in ASIC/SoC functional verification, including top-level verification of complex multi-IP designs or AI compute accelerators.

• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.

• Strong expertise in SystemVerilog, UVM (Universal Verification Methodology), assertion-based verification, and coverage-driven verification for complex hardware architectures.

• Strong collaborative mindset and problem-solving skills to work effectively with cross-functional FE Design, System, and SW teams.

• Fluency in English with excellent written and verbal communication skills.

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