Frontend RTL Designer for SoC & Chiplet Integration

Vertical Compute; Vlaams-Brabant; Sur place; EUR 65 000 - 90 000; Plein temps

Résumé du poste

Vertical Compute is seeking a Front-End RTL Designer to contribute to building our 3D-integrated chiplets and AI accelerator platforms. You will lead top-level SoC/chiplet integration, collaborating with verification and physical design teams to achieve target PPA metrics.

You should have a solid background in front-end RTL design (SystemVerilog/Verilog) and experience integrating IP blocks into unified silicon architectures, working in a fast-paced, collaborative hardware environment.

Qualifications

• Solid background in front-end RTL design and top-level SoC/chiplet integration.
• Degree in Electrical Engineering, Computer Engineering, Microelectronics, or related field.
• Strong SystemVerilog/Verilog skills and IP integration experience.
• Excellent collaboration and communication in a fast-paced hardware environment.

Responsabilités

• Lead top-level SoC and chiplet integration with internal and external IPs.
• Integrate VIM technology with compute engines to optimize throughput.
• Work with verification teams to build environments and debug RTL issues.
• Collaborate with physical design to meet PPA targets and timing closures.

Connaissances

Front-end RTL design

SoC/chiplet integration

IP integration

SystemVerilog/Verilog

Collaboration & communication

English language

Formation

Electrical/Computer Engineering or related field

Description du poste

Vertical Compute is seeking a Front-End RTL Designer to contribute to building our 3D-integrated chiplets and AI accelerator platforms. You will lead top-level SoC/chiplet integration, collaborating with verification and physical design teams to achieve target PPA metrics.

You should have a solid background in front-end RTL design (SystemVerilog/Verilog) and experience integrating IP blocks into unified silicon architectures, working in a fast-paced, collaborative hardware environment.