RTL Verification Engineer

Vertical Compute; Vlaams-Brabant; Sur place; EUR 65 000 - 90 000; Plein temps

Résumé du poste

Vertical Compute is seeking an RTL Verification Engineer to lead the verification of its 3D-integrated chiplets and VIM-enabled AI compute modules. You will drive top-level verification, develop advanced testbenches, and work closely with Front-End RTL, System Architecture, and Software teams to ensure tape-out readiness.

We seek a candidate with proven ASIC/SoC verification experience and strong SystemVerilog/UVM expertise, able to perform coverage-driven verification and root-cause debugging

Qualifications

• Proven ASIC/SoC verification experience.
• Experience with top-level verification of multi-IP designs.
• Strong SystemVerilog and UVM background.
• English fluency in written and spoken.

Responsabilités

• Lead top-level functional verification for the next-generation AI compute chiplet.
• Architect, deploy, and maintain SystemVerilog testbenches, assertions, and constrained-random plans.
• Drive coverage-driven verification and root-cause analysis across hardware/software boundaries.
• Collaborate with Front-End RTL Design, System Architecture, and Software teams for tape-out readiness.
• Benchmark system-level performance and validate post-silicon readiness.

Connaissances

SystemVerilog

UVM

Assertions

Coverage-driven verification

Formation

B.S./M.S./Ph.D. in Electrical Engineering or related

Description du poste

About Us

AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.

Why Now

After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.

About the role

We are looking for an RTL Verification Engineer to lead and execute the verification of our Vertical Compute's 3D-integrated chiplets. In this role, you will specifically focus on the top-level verification of the chiplets. Coupling high-performance AI accelerators directly with our proprietary Vertical Integrated Memory (VIM™), these chiplets showcase the full capabilities of our technology to address the AI market.

Key Responsibilities

• Lead top-level functional verification for our next-generation AI compute chiplet, ensuring complete protocol compliance and robust multi-die integration.


• Architect, deploy, and maintain advanced UVM/SystemVerilog testbenches, assertions, and constrained-random test plans for memory and compute subsystems.


• Drive coverage-driven verification, target debug, and root-cause analysis across complex hardware-software boundary scenarios.


• Collaborate closely with Front-End RTL Design, System Architecture, and Software/Compiler teams to achieve full tape-out readiness and post-silicon validation.


• Benchmark and analyze system-level performance to demonstrate the throughput, bandwidth, and energy efficiency of Vertical Compute's VIM™ technology.

About the team

This role is part of the Hardware Design team within Vertical Compute's Product & System organization, reporting directly to the HW Team Manager. You will work in close collaboration with the Front-End Design and Software teams, partnering across cross-functional engineering groups to ensure the seamless functionality, performance, and successful delivery of our vertical compute products.

About who you are

• Proven track record in ASIC/SoC functional verification, including top-level verification of complex multi-IP designs or AI compute accelerators.


• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.


• Strong expertise in SystemVerilog, UVM (Universal Verification Methodology), assertion-based verification, and coverage-driven verification for complex hardware architectures.


• Strong collaborative mindset and problem-solving skills to work effectively with cross-functional FE Design, System, and SW teams.


• Fluency in English with excellent written and verbal communication skills.

QUANTUM ROLE CONTEXT | Appended by Quantum.Jobs v2

Role context

This engineering role exists to validate functional digital logic and multi-die integrations before hardware fabrication. Situated within hardware engineering teams, the position operates between front-end design, system architecture, and software development groups. Professionals in this function construct verification environments, run simulation testbenches, and perform coverage analyses to detect design flaws early. By validating complex logical interactions across memory and compute interfaces, the role ensures integrated circuits meet architectural specifications and function properly upon physical deployment.

Quantum ecosystem relevance

While directly targeting high-performance semiconductor and artificial intelligence hardware architectures, functional verification methodologies remain essential to the broader advanced computing infrastructure. Next-generation quantum control systems and hybrid classical-quantum processors rely on highly integrated, low-latency microelectronic circuits to manage complex signal paths. Engineering functions focused on rigorous hardware verification support enabling technologies that bridge novel physical computing substrates with digital control architectures, facilitating reliable hardware execution across specialized computing platforms.

Capability signals

• Expertise in SystemVerilog and Universal Verification Methodology for complex digital architectures


• Proficiency in executing top-level functional verification and assertion-based test environments


• Practical experience conducting coverage-driven verification and root-cause hardware debugging