Senior FPGA Verification Engineer — RTL, UVM & Xilinx

Sapsol Technologies Inc; Melbourne; On-site; AUD 140,000 - 180,000; Full time

Job summary

Sapsol Technologies Inc. is seeking an expert FPGA verification engineer to join our design verification team in Melbourne. The role focuses on SystemVerilog/UVM-driven verification, FPGA lab testing, and collaboration with India GETC‑I for DO-254 process guidance.

The ideal candidate has 5+ years of experience in FPGA/ASIC verification, a STEM degree, and a proven track record with Xilinx platforms. Senior responsibilities include developing verification environments and ensuring robust

Qualifications

• Expert‑level verification engineer with strong SystemVerilog and/ or UVM experience.
• FPGA verification in lab testing and/or Hardware FPGA design verification testing.
• Experience with design on Xilinx products would be a strong plus.
• Ability to communicate with the India GETC‑I site and provide DO-254 guidance to the verification team.

Responsibilities

• RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
• Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
• Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing.

Skills

SystemVerilog

UVM experience

FPGA verification

Lab testing

Education

BSc in STEM

Tools

Xilinx

Verilog

VHDL

SystemVerilog

Job description

Required Skills:

• Expert‑level verification engineer with strong SystemVerilog and/ or UVM experience or
• FPGA verification in lab testing and/or Hardware FPGA design verification testing
• Experience with design on Xilinx products would be a strong plus
• expected to communicate effectively with emerging engineers at the India GETC‑I site and provide both technical and process (DO-254) guidance to the verification team.

Core Responsibilities

• RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
• Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
• Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. [1]

Key Qualifications

• Experience: Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).
• Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.