Staff Verification Engineer

IC Resources Recruitment; Town of Cambridge; On-site; AUD 171,722 - 219,423; Full time

Benefits offered by this job

Bonus opportunities

Benefits package

Job summary

IC Resources Recruitment is seeking a Staff Verification Engineer to join a stealth-like hardware team in Cambridge, working on quantum computing and next-generation systems. You will own verification across block, subsystem, and multi-FPGA designs, and develop scalable UVM environments in a collaborative, high-tech setting.

The role requires strong SystemVerilog, UVM, and programming skills (C/C++/Python). Visa sponsorship is available for UK-based candidates.

Qualifications

• Strong hands-on experience with SystemVerilog and UVM.
• Proven debugging skills across RTL, simulation and hardware.
• Experience owning verification planning and strategy in commercial settings.
• Ability to thrive in fast-paced environments with changing requirements.
• Familiarity with programming languages such as C, C++ or Python.
• Formal verification experience is a plus.

Responsibilities

• Lead the verification strategy and execution for block, subsystem, and multi-FPGA designs.
• Develop scalable and high-performance UVM environments to address complex architectures.
• Focus on verification with an emphasis on coverage, risk reduction, and system-level behavior.
• Collaborate closely with the Lead Verification Engineer and cross-functional hardware teams.
• Debug complex issues that span RTL, simulation, and hardware platforms.

Skills

SystemVerilog

UVM

C

C++

Python

Verification planning

Debugging

Job description

Staff Verification Engineer Overview

• Company Name: IC Resources Recruitment
• Job Role: Staff Verification Engineer
• Qualifications: Not Specified
• Category: IT Jobs
• Job Type: Full Time
• Location: Cambridge

An exciting opportunity has arisen for a Staff Verification Engineer to join a stealth-like hardware team in Cambridge, working at the forefront of quantum computing and next-generation systems design. This position offers a competitive salary ranging from £90,000 to £115,000, depending on experience, along with bonus opportunities and a comprehensive benefits package.

The successful candidate will take ownership of verification across block, subsystem, and multi-FPGA system-level designs. You will work in a deeply technical and highly collaborative environment, tackling complex hardware challenges and contributing to cutting-edge research. No prior experience in quantum computing is required; what is essential is a strong background in verification, curiosity, and a problem-solving mindset.

Key Responsibilities

• Lead the verification strategy and execution for block, subsystem, and multi-FPGA designs.
• Develop scalable and high-performance UVM environments to address complex architectures.
• Focus on verification with an emphasis on coverage, risk reduction, and system-level behavior.
• Collaborate closely with the Lead Verification Engineer and cross-functional hardware teams.
• Debug complex issues that span RTL, simulation, and hardware platforms.

Requirements

• Strong hands-on experience with SystemVerilog and UVM.
• Proven debugging skills across RTL, simulation, and hardware.
• Experience in owning verification planning and strategy in commercial settings.
• Ability to thrive in fast-paced environments with changing requirements.
• Familiarity with software or programming languages such as C, C++, or Python.
• Formal verification experience is a plus.

This role presents a unique chance to work on technology that is at the cutting edge of the industry, where your ideas and technical expertise will play a crucial role in shaping future developments. For those already based in the UK, visa sponsorship is available.

Degree Requirement: Not Specified

Visa Sponsorship May be