Senior ASIC Digital Design Engineer – Interconnect & NoC

Meta for Work; Redmond; On-site; AUD 253,000 - 356,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking highly skilled Design Engineers to join our team. You will contribute to the development of advanced technology solutions, including machine learning and network acceleration.

You will design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of devices and hardware. You will collaborate with researchers and engineers to design and verify complex IPs, drive micro-architecture and RTL design

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field.
• 8+ years of experience as Hardware Design Engineer for production silicon.
• Experience in digital design, RTL coding, and micro-architecture development.
• Ability to communicate design decisions to cross-functional partners.

Responsibilities

• Contribute to ASIC digital micro-architecture and design.
• Assist performance/power analysis and meet targets.
• Map algorithms onto hardware and specify IP/subsystem integration requirements.
• Collaborate with Verification, Physical Design, and Design-for-Test teams.
• Develop RTL, micro-architecture, and design verification for complex IPs.

Skills

ASIC architecture

RTL design

Power/perf analysis

Algorithm mapping

Cross-functional collaboration

8+ years hardware design experience

Education

Bachelor's degree in Computer Science/Engineering or related field

Job description

Meta is seeking highly skilled Design Engineers to join our team. You will contribute to the development of advanced technology solutions, including machine learning and network acceleration.

You will design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of devices and hardware. You will collaborate with researchers and engineers to design and verify complex IPs, drive micro-architecture and RTL design