Digital Design Engineer, Interconnect

Meta for Work; Redmond; On-site; AUD 253,000 - 356,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking highly skilled Design Engineers to join our team. You will contribute to the development of advanced technology solutions, including machine learning and network acceleration.

You will design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of devices and hardware. You will collaborate with researchers and engineers to design and verify complex IPs, drive micro-architecture and RTL design

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field.
• 8+ years of experience as Hardware Design Engineer for production silicon.
• Experience in digital design, RTL coding, and micro-architecture development.
• Ability to communicate design decisions to cross-functional partners.

Responsibilities

• Contribute to ASIC digital micro-architecture and design.
• Assist performance/power analysis and meet targets.
• Map algorithms onto hardware and specify IP/subsystem integration requirements.
• Collaborate with Verification, Physical Design, and Design-for-Test teams.
• Develop RTL, micro-architecture, and design verification for complex IPs.

Skills

ASIC architecture

RTL design

Power/perf analysis

Algorithm mapping

Cross-functional collaboration

8+ years hardware design experience

Education

Bachelor's degree in Computer Science/Engineering or related field

Job description

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Required Skills:

Contribute to ASIC digital µArchitecture and design

Assist performance/power analysis of the design and help meet power and performance targets

Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration

Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test

Develop micro-architecture, RTL coding, and design verification for complex IPs

Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads

Minimum Qualifications:

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

8+ years of experience as a Hardware Design Engineer for production silicon shipped in volume

Experience in digital design µArchitecture, RTL coding, and micro-architecture development

Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams

Preferred Qualifications:

Preferred Qualifications:

Experience with interconnect configurator and generation flows, and technically leading or mentoring engineers across deliverables

Experience collaborating with physical design and timing partners on interconnect implementation, including timing- and floorplan-aware microarchitecture, pipelining and repeater strategy, physical partitioning, clock- and power-domain crossings, and architecture versus physical implementation trade-offs to close frequency, area, and power targets

Experience defining fabric architecture and microarchitecture, including topology, address mapping, ordering and coherency requirements, buffering, quality-of-service, arbitration, and virtual-channel schemes, with industry-standard interconnect and bus protocols, and performance modeling and traffic-driven latency and bandwidth budgeting correlated against RTL results

Demonstrated experience developing interconnect/NoC/fabric IP from architecture specification through RTL delivery

Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)

Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)

Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Internet

Meta is proud to be an Equal Employment Opportunity and Aff

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

Digital Design Engineer, Interconnect Redmond, Western Australia, AU