Design Verification Engineer - Accelerators

Meta; Redmond; On-site; AUD 256,000 - 359,000; Full time

Benefits offered by this job

Equity

Bonus program

Benefits package

Job summary

Meta is hiring a Design Verification Engineer to own verification for accelerators, focusing on computer vision and imaging IPs. The role shapes verification strategy across IPs and builds scalable DV infrastructure across chips and programs, driving high-throughput verification with advanced techniques.

You will collaborate with architects, design, firmware, emulation, and physical design to ensure verification is integrated from the start.

Qualifications

• 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level.
• Has led DV for complex IP or an SoC through tape-out, including owning sign-off.
• Has defined and run verification plans, coverage strategies, and closure metrics across multiple blocks or IPs.
• Has built UVM verification environments from scratch and designed reusable verification components.
• Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification.
• Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows.
• Has led and mentored engineers and coordinated work across teams.

Responsibilities

• Shape architecture and microarchitecture decisions with architects and other teams for verification-aware design.
• Own DV for multiple complex IPs or subsystems from planning through sign-off.
• Define DV strategy across IPs, including simulation, formal, assertions, emulation and UPF verification.
• Design reusable testbench architectures and verification components shared across IPs and SoCs.
• Drive regression management, coverage analytics, and compute-efficient runs across growing designs.
• Identify DV quality gaps and lead initiatives to improve time-to-closure and DV methodologies, including AI-assisted approaches.
• Root-cause failures to RTL, reference models, or FW/SW and propose fixes.

Skills

SystemVerilog

UVM

C/C++

Python

DV infrastructure

Formal verification

SVA

Emulation

UPF (low-power)

Leadership / mentoring

Education

Bachelor's degree in Computer Science / Computer Engineering or related field

Bachelor's degree in Electrical Engineering / Computer Engineering or related field

Tools

Emulation platforms

FPGA prototyping

C/C++ toolchains

Job description

The AR glasses Meta is building run on custom silicon that delivers serious compute within a tight power budget. Our silicon team designs that silicon, with breakthrough work in computer vision, machine learning, imaging, and sensing. We're hiring a Design Verification (DV) lead to own verification for complex computer vision and imaging accelerator IP and subsystems. In this role, you'll define the verification strategy across multiple IPs and build DV infrastructure that scales across chips and programs.

Design Verification Engineer - Accelerators Responsibilities:

• Shape architecture and microarchitecture decisions with architects, design, FW/SW, emulation, physical design and post-silicon teams so the chip is designed with verification in mind. Work with TPMs on schedules and sign-off criteria
• Own DV for multiple complex IPs or subsystems from start to finish, all the way from verification planning through coverage closure and sign-off
• Define the strategy across IPs, including the mix of simulation (constrained-random, UVM), formal, assertions, emulation and FPGA prototyping, plus power-aware verification (UPF)
• Design reusable testbench architectures, verification IP and libraries that are shared across IPs, subsystems and SoC generations
• Drive regression management, automated triage, coverage analytics, and compute-efficient runs (simulation and emulation) so the team can sustain high throughput as the number of designs grows
• Spot verification-quality and productivity gaps across the org, lead initiatives that measurably improve quality and time-to-closure, and drive DV methodology improvements, including AI-assisted ones
• Root-cause failures down to specific lines of RTL, reference model or FW/SW, and propose the fixes

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
• 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level
• Has led DV for complex IP or an SoC through tape-out, including owning sign-off
• Has defined and run verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks or IPs
• Has built UVM verification environments from scratch and designed reusable verification components
• Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification
• Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows
• Has led and mentored engineers and coordinated work across teams

Preferred Qualifications:

• Has verified power-limited mobile, wearable or AR/VR System-on-Chips (SoCs)
• Has managed EDA vendors or contracted DV teams
• Has verified computer vision, imaging/ISP, DSP or ML accelerator designs
• Master's or PhD in EE/CE/CS
• Has rolled out methodology changes (formal, emulation, portable stimulus, ML/AI-assisted verification) across an org
• Has verified hardware against reference models written in C++ or Python, or co-simulated with firmware or software
• Has scaled DV infrastructure (regression farms, CI for hardware, coverage and triage dashboards) across multiple IPs or programs

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affi

Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$178,000/year to $250,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.