Senior Verification Engineer for RISC-V Cores (UVM, SystemVerilog)

TechBiz Global GmbH; Lavamünd; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

TechBiz Global is seeking a Senior Verification Engineer to join a client team developing RISC-V CPU cores. The role focuses on verifying complex digital designs at RTL using advanced methodologies.

You will work within the Verification Team on block/sub-system or top-level verification, employing SystemVerilog/UVM, scripting, and regression tools to ensure design correctness and reliability. English C1 and 8+ years industrial experience are required.

Qualifikationen

• Master or PhD required.
• English C1 proficiency.
• Industrial experience +8 years.
• Strong SystemVerilog and UVM knowledge.
• Proficient in Python, Perl, Bash and TCL; regression tools.
• Experience with simulation tools.
• Knowledge of revision control with Git and SVN.
• Experience in block/sub-system or top-level verification.
• Experience with formal and dynamic verification.
• Strong problem-solving skills and attention to detail.
• Excellent communication and teamwork abilities.

Kenntnisse

English C1

Ausbildung

Master or PhD

Tools

SystemVerilog

UVM

Python

Perl

Bash

TCL

Git

SVN

Jobbeschreibung

TechBiz Global is seeking a Senior Verification Engineer to join a client team developing RISC-V CPU cores. The role focuses on verifying complex digital designs at RTL using advanced methodologies.

You will work within the Verification Team on block/sub-system or top-level verification, employing SystemVerilog/UVM, scripting, and regression tools to ensure design correctness and reliability. English C1 and 8+ years industrial experience are required.