Senior Physical Verification Engineer IC Signoff

Ams Osram; Österreich; Remote; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

ams OSRAM is seeking a senior verification expert to drive physical verification signoff for advanced IC technologies within the LSP unit. You will develop and maintain DRC, LVS, ERC, antenna checks, and DFM rules, while leading automation efforts to improve efficiency and regression coverage.

The role requires 10+ years in semiconductors, strong understanding of CMOS layout and parasitics, and the ability to collaborate with layout, design, and technology teams to ensure tape-out readiness and

Qualifikationen

• Minimum 10 years in the semiconductor industry.
• Hands-on with physical verification tools and sign-off flows (DRC, LVS, ERC, DFM).
• Experience with automation and regression frameworks.
• Ability to explain verification findings to cross‑functional teams.

Aufgaben

• Develop and maintain verification rule decks (DRC, LVS, ERC, antenna) across multiple technologies.
• Execute physical signoff verification flows and ensure tape-out readiness.
• Create and optimize DFM and pattern-matching checks for manufacturability and yield.
• Investigate violations with root-cause analysis and collaborate with layout, design, and tech teams.
• Develop automation and regression frameworks to improve verification efficiency and traceability.
• Support technology qualification and methodology development for new process nodes.
• Integrate verification results into the overall signoff process and ensure robust flows.

Kenntnisse

IC Design Fundamentals

Semiconductor Manufacturing

Automation & Scripting

Problem Solving

Team Collaboration

Ausbildung

Master's degree in Electrical Engineering

Bachelor's degree in Microelectronics

Tools

Synopsys IC Validator

Siemens Calibre

Cadence PVS

Python/Tcl scripting

Jobbeschreibung

ams OSRAM is seeking a senior verification expert to drive physical verification signoff for advanced IC technologies within the LSP unit. You will develop and maintain DRC, LVS, ERC, antenna checks, and DFM rules, while leading automation efforts to improve efficiency and regression coverage.

The role requires 10+ years in semiconductors, strong understanding of CMOS layout and parasitics, and the ability to collaborate with layout, design, and technology teams to ensure tape-out readiness and