Senior Physical Verification Engineer (ICV & DFM)

Ams Osram; Premstätten; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

ams OSRAM’s LSP unit seeks a senior verification engineer to own and drive physical verification flows across multiple technologies. You will develop and maintain rule decks, run DRC/LVS/ERC, and deliver tape-out ready signoff through close collaboration with layout and design teams.

The ideal candidate holds a BSc/MSc in electrical engineering and has 10+ years in semiconductors, with strong scripting and automation skills, plus fluency in English (German a plus).

Qualifikationen

• Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or related field.
• 10+ years experience in semiconductor industry.
• Strong understanding of CMOS, layout, parasitics, reliability, and signoff requirements.
• Hands-on experience with Physical Verification tools, especially Synopsys IC Validator, and familiarity with DRC, LVS, ERC, Antenna, and DFM verification flows.
• Programming and automation skills in Python, Tcl, Perl, Shell, or SKILL.

Aufgaben

• Develop and maintain rule decks for DRC, LVS, ERC and antenna checks.
• Execute physical signoff verification flows and ensure tape-out readiness.
• Create and optimize DFM and pattern-matching checks to improve manufacturability.
• Investigate and resolve complex verification violations with root-cause analysis.
• Develop automation frameworks to improve verification efficiency and results tracking.
• Support technology qualification and methodology development for new process nodes.
• Integrate verification results into the overall signoff process.

Kenntnisse

IC Validator

DRC/LVS/ERC

Python scripting

Automation

Antenna/DFM

Silicon verification

Ausbildung

Electrical Engineering (BSc/MSc)

Tools

Synopsys IC Validator

Calibre

PVS

Jobbeschreibung

ams OSRAM’s LSP unit seeks a senior verification engineer to own and drive physical verification flows across multiple technologies. You will develop and maintain rule decks, run DRC/LVS/ERC, and deliver tape-out ready signoff through close collaboration with layout and design teams.

The ideal candidate holds a BSc/MSc in electrical engineering and has 10+ years in semiconductors, with strong scripting and automation skills, plus fluency in English (German a plus).