Lead Digital Verification Engineer — UVM & Testbench Expert

IC Resources; Bregenz; On-site; EUR 70,000 - 95,000; Full time

Job summary

IC Resources is seeking a Senior Digital Verification Engineer to join our team in Austria. This role focuses on leading UVM-based verification environments, pre-silicon checks, and robust testbench design for complex digital designs across automotive and industrial markets.

Ideal candidates have 5+ years in digital verification, strong SystemVerilog and Specman/e skills, and a track record of driving functional and code coverage closures.

Qualifications

• 5+ years of professional experience in Digital Verification.
• Bachelor's or Master's in Electrical Engineering or Physics.

Responsibilities

• Lead the development of UVM-based verification environments.
• Perform pre-silicon verification of digital and mixed-signal designs.
• Create verification plans in collaboration with design and systems teams.
• Implement automated checks and maintaining spec-to-coverage traceability.
• Define and drive functional and code coverage closure.
• Provide regular verification progress updates to stakeholders.
• Collaborate with design and systems teams to resolve bugs.
• Track bugs, functional coverage, and RTL code coverage.
• Mentor junior team members and drive process improvements.

Skills

UVM

Testbench architecture

SystemVerilog

Specman

e language

Education

Electrical Engineering or Physics

Tools

CAD tools

Job description

IC Resources is seeking a Senior Digital Verification Engineer to join our team in Austria. This role focuses on leading UVM-based verification environments, pre-silicon checks, and robust testbench design for complex digital designs across automotive and industrial markets.

Ideal candidates have 5+ years in digital verification, strong SystemVerilog and Specman/e skills, and a track record of driving functional and code coverage closures.