Senior Digital Verification Architect

Infineon Technologies AG; Villach; Híbrido; EUR 90.000 - 130.000; Jornada completa

Descripción de la vacante

Infineon Technologies AG in Villach, Austria, seeks a Senior Staff Engineer in Digital Verification to define verification plans and lead a team of verification engineers. You will develop verification environments in SystemVerilog/UVM, write tests for RTL and gate-level, and collaborate closely with architects and designers.

The role requires a university degree in electronics-related fields, 6+ years in digital verification, and strong SystemVerilog/UVM expertise.

Formación

• University degree in Electrical Engineering, Information Technology, Telematics, or a related field with a focus on electronics.
• At least 6 years of professional experience in digital verification, with experience in technical leadership highly desirable.
• Expert knowledge of SystemVerilog and UVM, and solid understanding of SystemVerilog for design.
• Strong scripting skills using technologies such as bash, tcsh, Python, TCL or similar.
• Knowledge of formal verification and mixed signal verification is an advantage.
• Fluent English language skills with German skills as a plus.

Responsabilidades

• Create and define verification plans for digital or digital mixed signal designs.
• Create new and improve existing verification environments in SystemVerilog/UVM.
• Write and execute tests for RTL and gate-level.
• Debug issues in design and verification environments.
• Lead and coordinate other verification engineers in your projects.
• Closely cooperate with architects, designers and other verification engineers.
• Mentoring of junior colleagues, consultants and students.
• Contribute to enhancement of existing methodologies and flows.

Conocimientos

SystemVerilog

UVM

Leadership

Scripting

RTL/ gate-level

English

German language

Educación

Electrical Engineering/IT degree

Descripción del empleo

Infineon Technologies AG in Villach, Austria, seeks a Senior Staff Engineer in Digital Verification to define verification plans and lead a team of verification engineers. You will develop verification environments in SystemVerilog/UVM, write tests for RTL and gate-level, and collaborate closely with architects and designers.

The role requires a university degree in electronics-related fields, 6+ years in digital verification, and strong SystemVerilog/UVM expertise.