Senior Digital Verification Engineer

IC Resources; Bregenz; On-site; EUR 70,000 - 95,000; Full time

Job summary

IC Resources is seeking a Senior Digital Verification Engineer to join our team in Austria. This role focuses on leading UVM-based verification environments, pre-silicon checks, and robust testbench design for complex digital designs across automotive and industrial markets.

Ideal candidates have 5+ years in digital verification, strong SystemVerilog and Specman/e skills, and a track record of driving functional and code coverage closures.

Qualifications

• 5+ years of professional experience in Digital Verification.
• Bachelor's or Master's in Electrical Engineering or Physics.

Responsibilities

• Lead the development of UVM-based verification environments.
• Perform pre-silicon verification of digital and mixed-signal designs.
• Create verification plans in collaboration with design and systems teams.
• Implement automated checks and maintaining spec-to-coverage traceability.
• Define and drive functional and code coverage closure.
• Provide regular verification progress updates to stakeholders.
• Collaborate with design and systems teams to resolve bugs.
• Track bugs, functional coverage, and RTL code coverage.
• Mentor junior team members and drive process improvements.

Skills

UVM

Testbench architecture

SystemVerilog

Specman

e language

Education

Electrical Engineering or Physics

Tools

CAD tools

Job description

Are you passionate about cutting-edge technologies and future-oriented projects in semiconductor design? We are seeking a highly skilled and motivated Senior Digital Verification Engineer to join our dynamic team. As a market leader in turnkey solutions, we work on a diverse range of products across Automotive, Compute, Industrial, Medical, and other markets. This role offers an exciting opportunity to contribute to innovative projects in a collaborative and supportive environment, with ample opportunities for professional growth.

Responsibilities

As a Senior Digital Verification Engineer, you will play a critical role in ensuring the functional correctness and quality of complex digital designs. Your key responsibilities will include:

• Leading the development of UVM-based verification environments
• Performing pre-silicon verification of digital and mixed-signal designs
• Creating detailed verification plans in collaboration with design and systems teams
• Implementing automated checks and maintaining spec-to-coverage traceability
• Defining and driving functional and code coverage closure
• Providing regular verification progress updates to stakeholders
• Collaborating with design and systems teams to resolve bugs
• Tracking bugs, functional coverage, and RTL code coverage
• Mentoring junior team members and driving continuous improvements in verification processes and tools

Education and Experience

• Bachelor's or Master's degree (or equivalent) in Electrical Engineering or Physics
• A minimum of 5 years of professional experience in Digital Verification

Technical Skills

• Expertise in advanced verification methodologies, particularly UVM
• Proven experience in designing and implementing testbench architectures
• Strong proficiency with verification languages such as SystemVerilog, Specman, or 'e'
• Familiarity with industry-standard CAD tools and verification flows