Principal Physical Verification Engineer (d/m/f)

Ams Osram; Premstätten; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

ams OSRAM’s LSP unit seeks a senior verification engineer to own and drive physical verification flows across multiple technologies. You will develop and maintain rule decks, run DRC/LVS/ERC, and deliver tape-out ready signoff through close collaboration with layout and design teams.

The ideal candidate holds a BSc/MSc in electrical engineering and has 10+ years in semiconductors, with strong scripting and automation skills, plus fluency in English (German a plus).

Qualifikationen

• Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or related field.
• 10+ years experience in semiconductor industry.
• Strong understanding of CMOS, layout, parasitics, reliability, and signoff requirements.
• Hands-on experience with Physical Verification tools, especially Synopsys IC Validator, and familiarity with DRC, LVS, ERC, Antenna, and DFM verification flows.
• Programming and automation skills in Python, Tcl, Perl, Shell, or SKILL.

Aufgaben

• Develop and maintain rule decks for DRC, LVS, ERC and antenna checks.
• Execute physical signoff verification flows and ensure tape-out readiness.
• Create and optimize DFM and pattern-matching checks to improve manufacturability.
• Investigate and resolve complex verification violations with root-cause analysis.
• Develop automation frameworks to improve verification efficiency and results tracking.
• Support technology qualification and methodology development for new process nodes.
• Integrate verification results into the overall signoff process.

Kenntnisse

IC Validator

DRC/LVS/ERC

Python scripting

Automation

Antenna/DFM

Silicon verification

Ausbildung

Electrical Engineering (BSc/MSc)

Tools

Synopsys IC Validator

Calibre

PVS

Jobbeschreibung

We are LSP - Light Sensors & Photonics, one of three business units within ams OSRAM, advancing the digitalization of light. At LSP, we go beyond traditional sensing-combining light, silicon, and system expertise to enable digital photonics solutions. Our focus is clear: powering next-generation applications in data centers, AR/VR, mobile and automotive, where light becomes a critical interface for data, perception, and interaction. This evolution marks a shift from components to integrated photonics systems -driving performance, scalability, and innovation in high-growth segments.

• Develop and maintain Synopsys IC Validator (ICV), Siemens Calibre, Cadence PVS rule decks for Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), and antenna verification across multiple semiconductor technologies
• Execute physical signoff verification flows using Synopsys IC Validator, Simens Calibre, Cadence PVS and analyze verification results to ensure tape-out readiness and compliance with foundry requirements
• Create and optimize DFM and pattern-matching checks to improve manufacturability, yield, reliability, and process robustness
• Investigate and resolve complex verification violations by performing root-cause analysis and collaborating closely with layout engineers, circuit designers, and technology teams
• Develop automation and regression frameworks to improve verification efficiency, rule quality, runtime performance, and result tracking
• Support technology qualification and methodology development by evaluating new process nodes, validating rule implementations, and establishing golden signoff flows
• Integrate verification results into the overall signoff process, including DRC, LVS, ERC, antenna, DFM, and parasitic extraction flows, ensuring a robust and scalable verification methodology

• Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or a related field
• Minimum of 10 years experience in semiconductor industry
• Strong understanding of semiconductor manufacturing and IC design fundamentals, including CMOS technologies, layout methodologies, parasitic effects, reliability, and signoff requirements
• Hands-on experience with Physical Verification tools, especially Synopsys IC Validator (ICV), and familiarity with DRC, LVS, ERC, Antenna, and DFM verification flows
• Programming and automation skills in languages such as Python, Tcl, Perl, Shell, or SKILL to develop verification utilities, regression frameworks, and automated workflows
• Strong analytical skills: ability to investigate complex DRC, LVS, ERC, and DFM violations, identify root causes, and develop effective solutions
• Attention to Detail: strong focus on accuracy and consistency, ensuring that even subtle rule violations or verification issues are identified before tape-out
• Able to work effectively across multidisciplinary teams, supporting design, layout, technology, reliability, and manufacturing groups
• Fluent English, German would be a beneficial but not a must. Ability to explain verification findings clearly to layout engineers, circuit designers, CAD teams, and foundry partners

We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). We offer a higher compensation depending on your expertise and skills.