Senior RF IC Package & PCB Layout Engineer

Ams Osram; Österreich; Remote; EUR 80.000 - 120.000; Vollzeit

Zusammenfassung

LSP – Light Sensors & Photonics, a unit within ams OSRAM, seeks an experienced RF/IC layout engineer in Austria. You will design RF substrates and PCB layouts for sensor and mixed-signal applications, focusing on signal integrity, EMI control, and robust manufacturability.

Collaborating with EMC, analog, package and IC teams, you will drive co-design efforts for chip-package-board integration and use Cadence/Altium tools for layout and verification.

Qualifikationen

• Bachelor's or Master's in Electrical Engineering or related field.
• Minimum of 6 years in Semiconductor/Electronic Industry.
• Experience with Cadence Allegro Suite and/or Altium Designer.
• Knowledge of RF/mixed-signal design and ESD/EMC concepts.
• Strong technical English; German is a plus.

Aufgaben

• Design and develop RF and high-frequency IC substrate and PCB layouts for sensor and mixed-signal applications.
• Perform RF-aware component placement and routing with controlled impedance, CPW, microstrip, and stripline.
• Optimize layout for SI/PI and RF performance, reducing crosstalk and EMI.
• Collaborate with EMC, analog, package, and IC design engineers for chip-package-board co-design.
• Support verification and manufacturability reviews, including DRC/ERC checks.
• Engage in supplier selection and qualification for PCB/SMT and provide assembly support.

Kenntnisse

English proficiency

RF design basics

Signal integrity awareness

Ausbildung

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Allegro Suite

Altium Designer

Cadence Virtuoso Suite

Siemens Calibre

Cadence PVS

Jobbeschreibung

LSP – Light Sensors & Photonics, a unit within ams OSRAM, seeks an experienced RF/IC layout engineer in Austria. You will design RF substrates and PCB layouts for sensor and mixed-signal applications, focusing on signal integrity, EMI control, and robust manufacturability.

Collaborating with EMC, analog, package and IC teams, you will drive co-design efforts for chip-package-board integration and use Cadence/Altium tools for layout and verification.