Wireless Radio Verification Engineer — UVM, Python, SoCs

Apple Inc.; Sunnyvale (CA); On-site; USD 122,700 - 214,300; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock programs

Job summary

Apple Inc. is seeking a Wireless Radio Verification Engineer in Sunnyvale, CA to verify Radio digital controllers and RF subsystems, building verification environments and test strategies for complex radio control paths.

You will own subsystem verification from test planning through coverage closure, collaborating with Design, RF, PHY, and Systems teams. Proficiency in SystemVerilog, UVM, and Python is valued, with opportunities for growth and a comprehensive benefits package.

Qualifications

• Bachelor's degree required.
• Knowledge of ASIC verification flows with SystemVerilog and UVM.
• Experience building verification environments and debugging.
• Experience with Verilog or VHDL.
• Proficiency in Python or similar scripting.
• Strong problem-solving and collaboration skills.

Responsibilities

• Verify Radio digital controllers or subsystems from test planning to feature closure.
• Develop UVM testbench environments and infrastructure for radio control and datapath subsystems.
• Implement constrained random scenarios exercising radio protocols, control sequences, and state machine interactions.
• Collaborate on digital + mixed-signal verification using SystemVerilog analog behavioral and/or DMS/real-number models to validate radio control paths.
• Drive closure by tracking regressions, debugging issues, and addressing coverage gaps.
• Partner with cross-functional Design, RF, and Systems teams to define verification strategy.
• Develop Python automation supporting verification flows and regression infrastructure.

Skills

SystemVerilog

UVM

RTL simulation

Python

Verilog/VHDL

Scripting languages

Education

Bachelor's degree

Tools

Python

Verilog

VHDL

Job description

Apple Inc. is seeking a Wireless Radio Verification Engineer in Sunnyvale, CA to verify Radio digital controllers and RF subsystems, building verification environments and test strategies for complex radio control paths.

You will own subsystem verification from test planning through coverage closure, collaborating with Design, RF, PHY, and Systems teams. Proficiency in SystemVerilog, UVM, and Python is valued, with opportunities for growth and a comprehensive benefits package.