VLSI RTL Design Engineer — High-Performance Cache & Fabric

Vaia GmbH; Fort Collins (CO); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD's Cores Organization seeks an experienced VLSI RTL design engineer to invent and implement high-performance Cache and Routing Fabric designs. The role is based in Fort Collins, CO, with potential relocation or travel to Austin, TX.

You will work with Cache and CPU Architects and collaborate across Design Verification, Physical Design, and Test teams. The ideal candidate has strong Verilog HDL skills, Digital RTL design experience, and a track record of cross-functional collaboration on

Qualifications

• Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience.
• Prior experience with Digital RTL Design, Verilog HDL, Software Development, and Scripting.
• BS/MS in EE, CS, CSE (or similar), plus 3+ years hardware design experience.

Responsibilities

• Collaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.
• Collaborate with Physical Design to develop RTL optimized for physical construction and timing closure.
• Collaborate with Design Verification to develop architecture and features that are clearly documented and verifiable.
• Collaborate with Design For Test teams to develop RTL that is reliable, testable, and manufacturable.
• Work across global teams to solve complex architectural interactions between IP and SOC designs.
• Improve CPU design quality and reduce design complexities through innovation and cross-team collaboration.
• Solve design and tool problems and create technical presentations for peers and management.

Skills

Digital RTL Design

Verilog HDL

Software Development

Scripting

Communication skills

Problem solving

Education

BS/MS in EE, CS, CSE

Job description

AMD's Cores Organization seeks an experienced VLSI RTL design engineer to invent and implement high-performance Cache and Routing Fabric designs. The role is based in Fort Collins, CO, with potential relocation or travel to Austin, TX.

You will work with Cache and CPU Architects and collaborate across Design Verification, Physical Design, and Test teams. The ideal candidate has strong Verilog HDL skills, Digital RTL design experience, and a track record of cross-functional collaboration on