Senior Cache RTL & CPU Microarchitecture Engineer

Advanced Micro Devices, Inc.; Fort Collins (CO); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD’s Cores Organization is seeking an experienced VLSI RTL Design Engineer to join as a senior technical contributor in Fort Collins, CO. You will design high-performance, energy-efficient Cache and Fabric solutions and contribute to next-generation cores and caches, mentoring other engineers while collaborating across disciplines.

The role emphasizes creativity, analysis, and problem-solving, with cross-functional teamwork to improve chip performance, power efficiency, and area.

Qualifications

• Bachelor’s or master’s degree in computer engineering, electrical engineering, or related field.
• Experience delivering complex RTL and cache designs.
• Strong analytical and collaborative skills.

Responsibilities

• Collaborate with Cache and CPU Architects to design optimized high-performance Cache and Routing Fabric designs.
• Collaborate with Physical Design teams to develop RTL optimized for physical implementation and timing closure.
• Collaborate with Design Verification teams to develop architectures that are clearly documented and verifiable.
• Collaborate with Design for Test teams to develop RTL that is reliable, testable, and manufacturable.
• Work across global teams to solve architectural interactions between IP and SoC designs.
• Develop improvements to CPU designs by increasing quality and simplifying design complexity through innovation.
• Create technical presentations for peers and management and mentor engineers.

Skills

Cache architecture

Cache Controller

RTL design

Verilog HDL

Scripting

CPU Coherency

NoC

Digital design

Education

Bachelor’s or Master’s degree in Computer/Electrical Engineering

Tools

Verilog HDL tools

Scripting languages

Job description

AMD’s Cores Organization is seeking an experienced VLSI RTL Design Engineer to join as a senior technical contributor in Fort Collins, CO. You will design high-performance, energy-efficient Cache and Fabric solutions and contribute to next-generation cores and caches, mentoring other engineers while collaborating across disciplines.

The role emphasizes creativity, analysis, and problem-solving, with cross-functional teamwork to improve chip performance, power efficiency, and area.