Senior VLSI Physical Design Engineer – High‑Speed Cores

AMD; Fort Collins (CO); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Career growth opportunities

Job summary

AMD, based in Fort Collins, Colorado, is seeking an experienced VLSI physical design engineer to lead high-speed design efforts for next-generation cores and caches. The role focuses on collaborating with RTL and physical designers across sites to optimize power, performance, area, and schedule.

The ideal candidate brings strong Verilog RTL comprehension, deep knowledge of VLSI methodologies, and a passion for innovation.

Qualifications

• Hands-on experience in high-speed VLSI design.
• Excellent understanding of computer architecture, hardware concepts, and design trade-offs.
• Knowledge of chip-level floor planning, bus/pin planning, clock tree synthesis, placement, optimization, routing, parasitic extraction, static timing analysis, IR-drop analysis, electromigration, physical verification, and sign-off.
• Ability to comprehend complex Verilog RTL and make minor modifications for timing or power.
• Knowledge of digital circuits, high-speed flops, synchronizers, level shifters, and SRAM.
• Familiarity with programming languages such as Perl, C, Tcl, etc.
• Experience with a variety of AI agents to increase engineering efficiency and automation.

Responsibilities

• Technical lead for high-speed VLSI design in deep submicron processes.
• Work closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule.
• Solve design and tool problems requiring ground-breaking approaches that utilize AI-native skills and champion innovation across the organization.
• Create technical presentations for peers and management.
• Guide and mentor junior engineers.

Skills

High-speed VLSI design

Computer architecture understanding

Design trade-offs

Education

BS/MS in EE, CS, CSE (or similar) preferred

Tools

Perl

C

Tcl

Job description

AMD, based in Fort Collins, Colorado, is seeking an experienced VLSI physical design engineer to lead high-speed design efforts for next-generation cores and caches. The role focuses on collaborating with RTL and physical designers across sites to optimize power, performance, area, and schedule.

The ideal candidate brings strong Verilog RTL comprehension, deep knowledge of VLSI methodologies, and a passion for innovation.