CPU Core RTL Design Engineer - High-Performance Pipelines

AMD; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

AMD in Austin is seeking a CPU Core RTL Design Engineer to help design and optimize next‑generation high‑performance processor cores. You will collaborate with architecture, performance, verification, and physical design teams to deliver scalable RTL, improve power, timing, and area, and contribute to core microarchitecture features.

This role offers exposure to client, server, and AI platforms across AMD, with opportunities to impact future CPU designs.

Qualifications

• Experience with Verilog/SystemVerilog RTL development in CPU/SoC/ASIC environments.
• Strong understanding of modern CPU architecture, especially out‑of‑order cores.
• Expertise in logic design and high‑speed processor pipeline development.
• Experience with load/store units or similar core subsystems.
• Knowledge of power‑efficient and low‑power design techniques, including timing and power optimization.
• Familiarity with synthesis, place‑and‑route, and timing closure.
• Experience debugging and optimizing designs in collaboration with performance and verification teams.
• Exposure to the full product lifecycle, from architecture through post‑silicon debug.
• Familiarity with physical design, scripting (e.g., Python, Tcl), and concepts such as DFT, clocking, reset, and power management.

Responsibilities

• Design and implement RTL for CPU core pipeline components and related logic.
• Contribute to microarchitecture definition for next‑generation processor cores.
• Collaborate with architecture, verification, and performance teams to deliver optimized designs.
• Analyze and improve performance, power, and timing characteristics.
• Support design verification, synthesis, timing closure, and physical design efforts.
• Debug and resolve pre‑silicon and post‑silicon issues.
• Partner with cross‑functional teams to align on design trade‑offs and execution.
• Contribute to scalable RTL methodologies, libraries, and best practices.

Skills

Verilog/SystemVerilog RTL development

CPU architecture

Logic design

Load/store units

Power optimization

Synthesis/place-and-route

Debugging with performance

DFT/clocking/reset/power management

Python

Tcl scripting

Education

Bachelor’s/Master’s/PhD in Electrical/Computer Engineering

Job description

AMD in Austin is seeking a CPU Core RTL Design Engineer to help design and optimize next‑generation high‑performance processor cores. You will collaborate with architecture, performance, verification, and physical design teams to deliver scalable RTL, improve power, timing, and area, and contribute to core microarchitecture features.

This role offers exposure to client, server, and AI platforms across AMD, with opportunities to impact future CPU designs.