VLSI Design Engineer - RTL, PPA & Silicon Bring-up

Retym, Inc; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Job summary

Retym, Inc is seeking a talented VLSI Design Engineer/Micro-architect in Austin, Texas. This role involves designing cutting-edge communication systems, collaborating on cross-functional teams, and participating in all design stages including RTL coding and verification.

The ideal candidate will have over 5 years of experience, strong skills in Verilog/System-Verilog, and a solid educational background in electrical or computer engineering. A self-motivated team player with good interpersonal skills is essential for success in this role.

Qualifications

• +5 years of experience as ASIC/VLSI digital design engineer.
• Strong Verilog/System-Verilog experience.
• Familiar with simulation tools/environments, verification methodologies.

Responsibilities

• Work closely with Algorithm and Architecture teams.
• Understand and translate high-level algorithmic requirements into hardware.
• Participate in all design stages: Micro-architecture definition, RTL coding, synthesis.

Skills

Verilog/System-Verilog

ASIC/VLSI Design

Simulation Tools

Interpersonal Skills

Self-motivated

Education

BS/MS in EE/CE from lead universities

Tools

Python

Perl

TCL

Job description

Retym, Inc is seeking a talented VLSI Design Engineer/Micro-architect in Austin, Texas. This role involves designing cutting-edge communication systems, collaborating on cross-functional teams, and participating in all design stages including RTL coding and verification.

The ideal candidate will have over 5 years of experience, strong skills in Verilog/System-Verilog, and a solid educational background in electrical or computer engineering. A self-motivated team player with good interpersonal skills is essential for success in this role.