Director of RTL & IP/VIP Engineering

Siemens EDA (Siemens Digital Industries Software); Austin (TX); On-site; USD 130,000 - 170,000; Full time

Benefits offered by this job

Competitive base salary

Bonus scheme

Generous holiday allowance

Pension

Private healthcare

Job summary

A global technology leader in Electronic Design Automation is seeking an experienced candidate for a role in Austin. This position requires over 15 years of expertise in RTL design and strong knowledge of SystemVerilog and UVM. The candidate will work alongside field engineers and customers to tackle deployment challenges and contribute to the development of verification IPs for cutting-edge technologies. A competitive salary and comprehensive benefits package are offered, reflecting the company's commitment to supporting its employees.

Qualifications

• 15+ years of experience in RTL design, IP/VIP development, verification, or emulation.
• Strong knowledge of SystemVerilog and UVM with experience in debugging and test plans.
• Understanding of bus protocols such as PCIe, CXL, USB, and Ethernet.

Responsibilities

• Work with field engineers and customers to resolve issues.
• Participate in the development of verification IPs for various interfaces.

Skills

SystemVerilog

UVM

RTL design

IP/VIP development

Debugging

Assertions

C/SystemC

Bus Protocols

Performance Metrics

Education

B.Tech/M.Tech in Electronics

Job description

A global technology leader in Electronic Design Automation is seeking an experienced candidate for a role in Austin. This position requires over 15 years of expertise in RTL design and strong knowledge of SystemVerilog and UVM. The candidate will work alongside field engineers and customers to tackle deployment challenges and contribute to the development of verification IPs for cutting-edge technologies. A competitive salary and comprehensive benefits package are offered, reflecting the company's commitment to supporting its employees.