Senior ASIC Verification Lead - RTL, UVM Strategy

Retym, Inc; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Retym, Inc is seeking a Verification Team-Leader in Austin, Texas to drive the RTL design verification of next-generation high-speed communication technology. The successful candidate will lead a team, define verification strategies, and mentor engineers in a fast-paced startup environment.

With a minimum of 10 years in digital design verification and proven management experience, you will ensure project milestones are met while fostering a culture of excellence and innovation.

Qualifications

• 10+ years of experience in digital design verification.
• 3+ years of experience managing or leading verification teams.
• Proven track record of completing two or more full block/system verification cycles.
• Strong knowledge of VLSI verification flows, concepts and methodologies.

Responsibilities

• Lead and manage a team of verification engineers.
• Define and execute verification strategies for complex digital blocks.
• Oversee development of robust verification environments.
• Collaborate with design engineers to debug issues.
• Foster a culture of technical excellence within the team.

Skills

Digital design verification

Team leadership

Problem-solving

SystemVerilog

UVM

Tools

SystemVerilog

UVM

Python

Perl

Job description

Retym, Inc is seeking a Verification Team-Leader in Austin, Texas to drive the RTL design verification of next-generation high-speed communication technology. The successful candidate will lead a team, define verification strategies, and mentor engineers in a fast-paced startup environment.

With a minimum of 10 years in digital design verification and proven management experience, you will ensure project milestones are met while fostering a culture of excellence and innovation.