ASIC Design Engineer Intern (Video Silicon IP) - 2027 Summer

Centro Escolar University; San Jose (CA); On-site; USD 51,000 - 73,000; Part time

Benefits offered by this job

Health insurance

Life insurance

Wellbeing benefits

10 paid holidays per year

Paid sick time

Housing allowance eligibility for_int

Job summary

Centro Escolar University seeks candidates for a video silicon IP role in San Jose, CA. You will design accelerators for video encoding and processing as part of the Video Silicon IP team, collaborating with architecture, algorithm, and verification groups to deliver high-performance, low-power ASIC IPs.

Applicants should be pursuing a Master’s degree in CS or EE, possess knowledge of video codecs, and have experience with SystemVerilog/HLS, UVM, SystemC, or DPI.

Qualifications

• Pursuing a Master’s degree in computer science, electrical engineering, or a related technical discipline.
• Knowledge of video codecs.
• Experience with RTL design using SystemVerilog or High-Level Synthesis (HLS).
• Experience with UVM methodology, SystemC, or DPI.
• Good programming skills in Python for task automation.

Responsibilities

• Design hardware accelerators for advanced video encoding and processing as part of the Video Silicon IP team.
• Collaborate closely with architecture, algorithm, and verification teams to build high-performance and low-power video processing ASIC IPs.
• Apply knowledge of computer architecture and ASIC design to create designs for compressing and processing still images and videos.

Skills

Video codecs

Python programming

Education

Master's degree in CS/EE or related

Tools

SystemVerilog

HLS

UVM

SystemC

DPI

Job description

Your Role

Here’s what you will be doing:

• Design hardware accelerators for advanced video encoding and processing as part of the Video Silicon IP team.
• Collaborate closely with architecture, algorithm, and verification teams to build high-performance and low-power video processing ASIC IPs.
• Apply knowledge of computer architecture and ASIC design to create designs for compressing and processing still images and videos.

About You

The company is looking for candidates with the following qualifications:

• Currently pursuing a Master's degree in computer science, electrical engineering, or a related technical discipline.
• Knowledge of video codecs.
• Experience with RTL design using SystemVerilog or High-Level Synthesis (HLS).
• Experience with UVM methodology, SystemC, or DPI.
• Good programming skills in Python for task automation.

Compensation & Benefits

• Hourly rate of $45.
• Day one access to health insurance, life insurance, and wellbeing benefits.
• 10 paid holidays per year.
• Paid sick time (56 hours if hired in the first half of the year, 40 hours if hired in the second half).
• Housing allowance eligibility for interns not working 100% remotely.