Video ASIC Design Intern — RTL/HLS & Silicon IP

LPU Batangas; San Jose (CA); On-site; USD 51,000 - 73,000; Full time

Benefits offered by this job

Health insurance

Wellbeing benefits

Housing allowance eligibility

Paid holidays

Paid sick time

Job summary

LPU Batangas is seeking an undergraduate intern to design hardware accelerators for video encoding and processing as part of the Video Silicon IP team. You will collaborate with architecture, algorithm, and verification groups to build high-performance, low-power ASIC IPs.

The role requires knowledge of video codecs, RTL design with SystemVerilog or HLS, UVM/SystemC/DPI, and strong Python scripting for automation. Day one benefits apply to interns where eligible.

Qualifications

• Pursuing an undergraduate degree in CS, EE, or related technical discipline.
• Knowledge of video codecs and ASIC design concepts.
• Experience with RTL design using SystemVerilog or HLS.
• Exposure to UVM, SystemC, or DPI.
• Good Python programming for automation.

Responsibilities

• Design hardware accelerators for video encoding and processing within a Video Silicon IP team.
• Collaborate with architecture, algorithm, and verification teams to build high-performance, low-power video processing ASIC IPs.
• Apply computer architecture and ASIC design knowledge to create designs for compressing/processing still images and videos.

Skills

Video codecs

SystemVerilog

HLS

UVM

Python

Education

Undergraduate degree in computer science or electrical engineering

Job description

LPU Batangas is seeking an undergraduate intern to design hardware accelerators for video encoding and processing as part of the Video Silicon IP team. You will collaborate with architecture, algorithm, and verification groups to build high-performance, low-power ASIC IPs.

The role requires knowledge of video codecs, RTL design with SystemVerilog or HLS, UVM/SystemC/DPI, and strong Python scripting for automation. Day one benefits apply to interns where eligible.