Video Codec Algorithm Modeler for HW/ASIC Accelerators

ByteDance; San Jose (CA); On-site; USD 218,000 - 480,000; Full time

Job summary

ByteDance in the United States is seeking a video codec algorithm modeling engineer to design algorithms and C-models for hardware-accelerated encoding and processing.

You will work with a cross-functional team spanning algorithm, architecture, software, firmware, and hardware design to deliver scalable solutions for billions of users.

Applicants should have a BS degree in ECE/CS, strong knowledge of AVC/HEVC/AV1, and proven experience in C/C++ signal processing.

Qualifications

• BS degree or above in Electrical/Computer Engineering, Computer Science, or equivalent fields
• Strong knowledge in video coding standards (AVC/H.264, HEVC/H.265, AV1, and VVC etc.)
• Solid experience in the development of video/image signal processing algorithms in C/C++
• Collaborative mindset, with solid written and verbal communication skills

Responsibilities

• Design and develop algorithms and C/C++ models for advanced video encoding and processing for hardware implementation
• Support use of C/C++ models for architectural modeling and algorithm benchmarking
• Collaborate with the HW architecture and design team for optimal algorithm and architecture co-design

Skills

C/C++ programming

Video coding standards

Algorithms design

Communication skills

Education

BS in Electrical/Computing/CS

Tools

SystemC modeling

HW architecture collaboration

Job description

ByteDance in the United States is seeking a video codec algorithm modeling engineer to design algorithms and C-models for hardware-accelerated encoding and processing.

You will work with a cross-functional team spanning algorithm, architecture, software, firmware, and hardware design to deliver scalable solutions for billions of users.

Applicants should have a BS degree in ECE/CS, strong knowledge of AVC/HEVC/AV1, and proven experience in C/C++ signal processing.