Video ASIC Design Intern: Hardware Accelerators

ByteDance; San Jose (CA); Hybrid; USD 34,000 - 55,000; Full time

Job summary

ByteDance in San Jose is seeking an intern for our Video Silicon IP team. You will collaborate with architecture, algorithm and verification to design hardware accelerators for video encoding and processing, gaining hands-on experience on ASIC/FPGA projects.

Ideal candidates are undergraduates in CS/EE, have knowledge of video codecs, RTL design (SystemVerilog), and Python for automation. This internship offers practical industry exposure, workshops, and the opportunity to contribute to

Qualifications

• Pursuing an undergraduate degree in CS/EE or related technical field.
• Knowledge of video codecs.
• Experience with RTL design (SystemVerilog) or High Level Synthesis (HLS).
• Experience with UVM, SystemC, or DPI.
• Strong Python programming for automation.

Responsibilities

• Interns will work with ASIC design teams to build high-performance video processing IPs.
• Support design, verification, and optimization of video codecs for ASIC/FPGA.
• Assist in benchmarking and validating IP under real workloads.

Skills

Video codecs

RTL design

Python

UVM/SystemC/DPI

Education

Undergraduate in CS/EE or related technical discipline

Tools

SystemVerilog

UVM

SystemC

Job description

ByteDance in San Jose is seeking an intern for our Video Silicon IP team. You will collaborate with architecture, algorithm and verification to design hardware accelerators for video encoding and processing, gaining hands-on experience on ASIC/FPGA projects.

Ideal candidates are undergraduates in CS/EE, have knowledge of video codecs, RTL design (SystemVerilog), and Python for automation. This internship offers practical industry exposure, workshops, and the opportunity to contribute to