Verification Platform Architect - High-Throughput RTL

Apple Inc.

Austin, Northern (TX, KY)

Hybrid

USD 140,000 - 210,000

Full time

14 days+
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Job summary

Apple Inc. seeks a Verification Platform Engineer for Platform Architecture to advance high‑performance RTL simulation tooling and DV workflows.

You will own engagements with silicon engineering, modify testbenches, and improve throughput through infrastructure improvements and platform R&D. Ideal candidates have a BS in EE/CE, strong SystemVerilog and EDA tooling experience, and hands‑on DV methods (UVM, DPI‑C).

Qualifications

  • Bachelor's degree in Computer Engineering, Electrical Engineering, or related field.
  • SystemVerilog and EDA tooling experience required.
  • Software development experience (C++), scripting (Perl or Python).

Responsibilities

  • Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling.
  • Modify testbench and design RTL for tool compatibility and simulation efficiency.
  • Use internal and external EDA tools to diagnose issues and explore design alternatives.
  • Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes.
  • Partner with internal teams for focused, high-impact engagements.
  • Occasionally travel within the US (about once a year).

Skills

SystemVerilog
C++ programming
Python scripting
DPI-C
UVM
Testbench architecture
Hardware verification

Education

Bachelor's degree in Computer/Electrical Engineering
Master’s degree (preferred)

Tools

RTL simulation tools
LEC
Waveform debugging
EDA tooling

Job description

Apple Inc. seeks a Verification Platform Engineer for Platform Architecture to advance high‑performance RTL simulation tooling and DV workflows.

You will own engagements with silicon engineering, modify testbenches, and improve throughput through infrastructure improvements and platform R&D. Ideal candidates have a BS in EE/CE, strong SystemVerilog and EDA tooling experience, and hands‑on DV methods (UVM, DPI‑C).

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