Top-Level CPU Verification Engineer (RTL & Testbench)

Apple Inc.; Santa Clara (CA); On-site; USD 129,300 - 194,700; Full time

Benefits offered by this job

Stock programs

Relocation assistance

Medical & dental coverage

Job summary

Apple Inc. in Santa Clara, California, is seeking a verification engineer to help define verification methodology for low power complex processor designs. You will collaborate with RTL designers and verification engineers to build robust test environments and flows.

The role emphasizes SystemVerilog, C/C++, Python, and testbench development, plus coverage analysis and regression testing. Apple offers comprehensive benefits and relocation support where applicable.

Qualifications

• BS in Electrical Engineering, Computer Science, or Computer Engineering preferred.
• Strong understanding of processor design, instruction set architectures, pipeline design, cache hierarchies, and memory systems.
• RTL development – Experience creating efficient, synthesizable RTL code with timing closure, area optimization, and power‑aware design techniques.
• SystemVerilog – Proficiency in SystemVerilog including interfaces, assertions, and verification constructs. Ability to write clean, maintainable HDL code for both design and verification
• Programming/scripting skills (C, C++, Python) – Strong software development capabilities for automation and tool development. C/C++ experience with embedded programming and hardware interfaces. Python proficiency for scripting, design automation, and EDA tool integration
• Problem solving skills – Analytical thinking and systematic approach to complex hardware design and verification challenges
• Testbench Setup and Build Experience – Experience with build systems, regression frameworks, and maintaining verification infrastructure. Ability to set up automated testing flows and integrate with CI systems
• Random Regression and Failure Analysis Experience running large-scale random regression suites and systematically analyzing test failures. Skilled in debugging complex simulation issues, identifying root causes, and distinguishing between design bugs, testbench issues, and tool problems
• Driving Coverage Convergence Expertise – Experience developing coverage models, analyzing coverage gaps, and creating targeted tests to improve coverage metrics. Ability to work with design teams to achieve verification closure and sign-off criteria
• Be an outstanding teammate with excellent communication skills and the desire to address diverse challenges

Responsibilities

• Work closely with verification engineers and RTL designers on defining effective verification methodology for low power complex processor design
• Develop test plans, test benches, and test environments
• Develop tests in assembly, and C/C++
• Drive and develop the tools and flows for advanced verification methodology
• Develop, verify, and maintain efficient testbench environments
• Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered

Skills

C/C++

SystemVerilog

Python

RTL development

Verification methodologies

Testbench development

Debugging

CI / regression testing

Waveform analysis

Communication

Education

BS in Electrical Engineering, Computer Science, or Computer Engineering

Tools

Build systems

Regression frameworks

Waveform analysis tools

Job description

Apple Inc. in Santa Clara, California, is seeking a verification engineer to help define verification methodology for low power complex processor designs. You will collaborate with RTL designers and verification engineers to build robust test environments and flows.

The role emphasizes SystemVerilog, C/C++, Python, and testbench development, plus coverage analysis and regression testing. Apple offers comprehensive benefits and relocation support where applicable.