RTL Verification Engineer - Memory & Cache Systems

Apple Inc.; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking an experienced RTL verification engineer to validate design functionality, implement testbenches with SystemVerilog and UVM, and ensure compliance with architectural specs.

You will run and debug simulations, generate coverage analyses, and refine testbenches for reusable, scalable verification workflows across SRAMs, register files, and caches. Collaboration with circuit teams and use of industry tools are essential.

Qualifications

• RTL verification testbenches using SystemVerilog/Verilog.
• UVM-based verification environments with monitors and scoreboards.
• Verify memory blocks (SRAM, register files) and timing.
• Use Python/Perl/C++ to automate verification flows.
• Familiar with waveform tools for debugging.

Responsibilities

• Develop and maintain testbenches for RTL verification.
• Run simulations, triage failures, and track bugs.
• Analyze coverage and debug results to ensure high-quality verification.
• Refactor testbench code to improve reusability and maintainability.
• Collaborate with circuit designers and RTL teams across Apple Silicon projects.

Skills

SystemVerilog

Verilog

UVM

Python

Perl

C++

Regression testing

Waveform debugging

Timing analysis

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Verdi

Cadence Indago

Job description

Apple Inc. in Austin, Texas is seeking an experienced RTL verification engineer to validate design functionality, implement testbenches with SystemVerilog and UVM, and ensure compliance with architectural specs.

You will run and debug simulations, generate coverage analyses, and refine testbenches for reusable, scalable verification workflows across SRAMs, register files, and caches. Collaboration with circuit teams and use of industry tools are essential.