Verification Platform Architect: High-Performance DV Tooling

Apple Inc.; Cupertino (CA); On-site; USD 180,000 - 320,000; Full time

Job summary

Apple’s Platform Architecture group seeks a Verification Platform Engineer to advance DV methodologies and tooling for Apple silicon. You will enable faster simulation throughput via testbench design, infrastructure improvements, and platform R&D, working with silicon engineering and internal teams.

Qualifications include a Bachelor’s in computer/electrical engineering, SystemVerilog and EDA tooling experience, plus C++ and Python scripting. Travel to US sites may occur annually.

Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field (or equivalent practical experience).
• Experience with SystemVerilog and EDA tooling.
• Experience with software development (C++ etc.) and scripting (Perl or Python).

Responsibilities

• Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling.
• Modify testbench and design RTL for tool compatibility and simulation efficiency.
• Use internal and external EDA tools (e.g., RTL simulation tools, LEC, wave dumps, design libraries) to diagnose issues and explore design alternatives.
• Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes.
• Partner closely with internal teams for focused, high-impact engagements.
• Occasionally travel (~once a year) to collaborate with development groups within the US.

Skills

SystemVerilog

C++

Python

Communication

Education

Bachelor's in Computer/Electrical Engineering

Master's degree (preferred)

Tools

SystemVerilog tooling

EDA tooling

LEC

Wave dumps

RTL simulation tools

Perl

Python

C++

Job description

Apple’s Platform Architecture group seeks a Verification Platform Engineer to advance DV methodologies and tooling for Apple silicon. You will enable faster simulation throughput via testbench design, infrastructure improvements, and platform R&D, working with silicon engineering and internal teams.

Qualifications include a Bachelor’s in computer/electrical engineering, SystemVerilog and EDA tooling experience, plus C++ and Python scripting. Travel to US sites may occur annually.