Digital Verification Engineer

efficientcomputer; San Francisco (CA); On-site; USD 130,000 - 180,000; Full time

Benefits offered by this job

Equity

401(k) match

Comprehensive benefits

Bonus

Job summary

Efficient Computer in San Francisco, CA, is seeking a Design Verification Engineer to own functional verification of SoC blocks using Fabric technology. You will build testbenches, write plans, and drive coverage with senior DV engineers, RTL designers, and architects as products move toward volume production.

You will develop UVM/SystemVerilog testbenches, write assertions and coverage models, and debug issues with designers.

Qualifications

• 4+ years of ASIC/SoC design verification experience.
• Experience building and extending UVM testbenches (agents, scoreboards, sequences).
• Experience defining functional coverage and driving coverage closure.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specs in collaboration with design/architecture teams.
• Write SystemVerilog assertions and coverage models and drive closure to goals.
• Debug simulation failures with designers to root-cause issues.
• Contribute to regression infrastructure, automation, and dashboards to track verification progress.
• Support gate-level simulation and other sign-off activities.

Skills

UVM SystemVerilog

Python

Debugging

Scripting & Automation

Communication

Education

Bachelor's in Electrical/Computer Engineering

Master's or PhD in Electrical/Computer Engineering

Tools

UPF

Job description

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10-100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks-unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We are looking for a Design Verification Engineer to join our newly formed verification team and own the functional verification of blocks and subsystems in our SoC, including Efficient's proprietary Fabric technology. You'll work alongside senior DV engineers, RTL designers, and architects to build testbenches, close coverage, and find bugs before silicon does. This is a great opportunity to grow your skills while having a real influence on our products and processes as we move from initial product development to market release and scaled volume production.

What You'll Do

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specifications in collaboration with design and architecture teams.
• Write SystemVerilog assertions and functional coverage models, and drive coverage to closure.
• Debug simulation failures, working with designers to root-cause and fix issues.
• Contribute to regression infrastructure, automation, and dashboards that track verification progress.
• Support gate-level simulation and other sign-off activities.

Required Qualifications & Experience

• Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout.
• UVM and SystemVerilog: Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests.
• Coverage: Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
• Assertions: Working knowledge of SystemVerilog Assertions.
• Debug Skills: Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
• Scripting & Automation: Proficiency in Python for test automation, log analysis, and regression flows.
• Communication: Ability to clearly report verification status and issues to the team.

Ways to Stand Out

• C/C++ experience for reference models or DPI-based verification.
• Exposure to formal verification (JasperGold or similar).
• Experience building or using AI agentic flows for DV.
• Knowledge of computer architecture or dataflow architectures.
• Exposure to power-aware verification (UPF)

We offer a competitive base salary for this role, generally ranging from $130,000 to $180,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.

Why Join Efficient?

Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility-plus opportunities to grow your skills and career as we scale.