Senior Verification Engineer: UVM/SoC for AI Fabric

efficientcomputer; San Francisco (CA); On-site; USD 130,000 - 180,000; Full time

Benefits offered by this job

Equity

401(k) match

Comprehensive benefits

Bonus

Job summary

Efficient Computer in San Francisco, CA, is seeking a Design Verification Engineer to own functional verification of SoC blocks using Fabric technology. You will build testbenches, write plans, and drive coverage with senior DV engineers, RTL designers, and architects as products move toward volume production.

You will develop UVM/SystemVerilog testbenches, write assertions and coverage models, and debug issues with designers.

Qualifications

• 4+ years of ASIC/SoC design verification experience.
• Experience building and extending UVM testbenches (agents, scoreboards, sequences).
• Experience defining functional coverage and driving coverage closure.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specs in collaboration with design/architecture teams.
• Write SystemVerilog assertions and coverage models and drive closure to goals.
• Debug simulation failures with designers to root-cause issues.
• Contribute to regression infrastructure, automation, and dashboards to track verification progress.
• Support gate-level simulation and other sign-off activities.

Skills

UVM SystemVerilog

Python

Debugging

Scripting & Automation

Communication

Education

Bachelor's in Electrical/Computer Engineering

Master's or PhD in Electrical/Computer Engineering

Tools

UPF

Job description

Efficient Computer in San Francisco, CA, is seeking a Design Verification Engineer to own functional verification of SoC blocks using Fabric technology. You will build testbenches, write plans, and drive coverage with senior DV engineers, RTL designers, and architects as products move toward volume production.

You will develop UVM/SystemVerilog testbenches, write assertions and coverage models, and debug issues with designers.