Verification Engineer

TPI Global Solutions; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Job summary

TPI Global Solutions in San Jose seeks an experienced verification engineer to participate in the functional verification of ASIC/SoC blocks within a CPU/GPU development effort. You will document and execute test plans with directed and constrained-random tests, adapt to evolving industry verification methods, and collaborate across design and verification teams.

Requirements include 10+ years in verification, strong C/C++ in Linux, proficiency with Verilog/SystemVerilog/SystemC, DPI/PLI, and

Qualifications

• 10+ years of proven verification experience on large ASIC projects.
• Strong C/C++ development in Linux environments.
• Expertise with debugging tools such as GDB and Valgrind.
• Proficient in Object Oriented programming, STL, architecture and data structures.
• Knowledge of Perl and Makefiles.
• Experience with Verilog/SystemVerilog/SystemC; DPI/PLI experience preferred.
• Strong analytical skills and attention to detail.
• Excellent written and verbal communication skills.

Responsibilities

• Participate in functional verification of ASIC/SoC blocks for CPU/GPu development.
• Document and execute test plans using directed and constrained-random tests.
• Adopt evolving verification methodologies and contribute to verification infrastructure.
• Collaborate with design and verification teams to understand and verify designs.

Skills

C/C++ development

Linux environment

Debugging with GDB/Valgrind

Object oriented programming

STL

Computer architecture

Perl

Makefiles

Verilog/SystemVerilog/SystemC

DPI/PLI

Analytical skills

Communication skills

Tools

GDB

Valgrind

DPI/PLI tooling

Verilog/SystemVerilog tooling

Job description

• Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
• Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
• Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
• Be familiar with hardware modeling and/or assertion-based verification methods.

Experience And Education:

• 10+ years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
• Strong background in C/C++ development in a Linux Environment.
• Strong debug skills and experience with debug tools such as Gdb, Valgrind.
• Proficient in Object Oriented programming, STL, computer architecture and data structures.
• Knowledge of Perl and Makefiles.
• Experience in Verilog/SystemVerilog/SystemC, preferred.
• Experience in C/Verilog environment using DPI/PLI, preferred.
• Strong analytical skills and attention to detail.
• Excellent written and communication skills.