Senior DV engineer

Mirafra Technologies; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

Mirafra Technologies seeks a senior design verification engineer to lead verification efforts for AI/Data Center SoCs. You will develop verification strategies, create UVM environments, and drive coverage closure in collaboration with architects and designers.

You will debug RTL, run constrained-random tests, and contribute to regression and automation, leveraging SystemVerilog, UVM, and high-speed interface verification.

Qualifications

• 7+ years of Design Verification experience in complex ASIC/SoC designs.
• Strong hands-on SystemVerilog and UVM experience.
• Experience developing verification environments, test plans, sequences, scoreboards, assertions, and coverage models.
• Strong debugging skills with industry-standard simulation and waveform tools.
• Experience with SoC/interconnect and high-speed interface verification.
• Solid understanding of digital design, computer architecture, and ASIC verification methodologies.

Responsibilities

• Develop and execute comprehensive design verification strategies and test plans for AI/Data Center SoCs.
• Develop SystemVerilog/UVM-based verification environments, testbenches, sequences, and checkers.
• Create functional and constrained-random tests and drive coverage closure.
• Debug RTL, simulation failures, and complex functional issues with design and architecture teams.
• Perform block, subsystem, and SoC-level verification.
• Collaborate with architects and designers to understand specs and ensure complete verification coverage.
• Analyze coverage metrics and drive code, functional, and assertion coverage to closure.
• Participate in regression development, automation, and verification infrastructure improvements.

Skills

SystemVerilog

UVM

Verification environments

Test plans

Sequences

Scoreboards

Assertions

Coverage models

Debugging skills

SoC interconnect

Tools

C/C++ or Python

Job description

• Develop and execute comprehensive design verification strategies and test plans for AI/Data Center SoCs.
• Develop SystemVerilog/UVM-based verification environments, testbenches, sequences, and checkers.
• Create functional and constrained-random tests and drive coverage closure.
• Debug RTL, simulation failures, and complex functional issues in collaboration with design and architecture teams.
• Perform block, subsystem, and SoC-level verification.
• Work closely with architects and designers to understand specifications and ensure complete verification coverage.
• Analyze coverage metrics and drive code, functional, and assertion coverage to closure.
• Participate in regression development, automation, and verification infrastructure improvements.

Required Qualifications

• 7+ years of experience in Design Verification of complex ASIC/SoC designs.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience developing verification environments, test plans, sequences, scoreboards, assertions, and coverage models.
• Strong debugging skills using industry-standard simulation and waveform-debug tools.
• Experience with SoC/interconnect and high-speed interface verification.
• Strong understanding of digital design, computer architecture, and ASIC verification methodologies.

Preferred Qualifications

• Experience with Ethernet verification.
• Experience with PCIe verification.
• Experience with AI/ML accelerators, Data Center SoCs, networking chips, or high-performance computing architectures.
• Experience with C/C++ or Python for verification and automation.
• Experience with formal verification, emulation, or hardware acceleration is a plus