ASIC Verification Engineer

Dexian DISYS; Santa Clara (CA); On-site; USD 103,000 - 110,000; Full time

Job summary

Dexian DISYS is seeking an ASIC Verification Engineer in Santa Clara, CA to drive block-level functional verification for advanced CPU/GPU SoCs using directed and constrained-random simulation. Expect collaboration with design and verification teams to ensure robust silicon.

Must have 5-7 years experience, expert C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog; Formal Verification background preferred. This is a contract role with competitive hourly pay.

Qualifications

• 5-7 years experience, expert C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog.

Responsibilities

• Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random simulation.

Skills

C/C++ in Linux

Verilog/SystemVerilog

OOP/STL

Job description

ASIC Verification Engineer

Santa Clara, CA

12 + Months

$75 – $80/HR

Role:

Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random simulation.

Must Have:

5-7 years experience, expert C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog (Formal Verification / 7+ years preferred).

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.