Design Verification Engineer

Eridu; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Eridu in San Francisco, CA seeks an experienced ASIC verification lead to design and implement verification strategies for data‑center networking ASICs. You will drive gate‑level simulations, coverage analysis, and verification planning, collaborating with design and software teams.

The role requires 8–15 years of hands‑on experience, a strong background in SystemVerilog/UVM, and expertise in Ethernet and PCIe protocols, with excellent communication to coordinate complex issues.

Qualifications

• ME/BE in Electrical Engineering, Computer Engineering, or related field.
• 8–15 years of ASIC verification experience in data center networking.
• Expertise in Hardware Verification and Hardware Verification Methodology (e.g., SystemVerilog, OVM/VMM/UVM).
• Experience with functional coverage, gate/timing/power simulations, constrained random verification, and test‑plan documentation.
• Python/Perl/Tcl experience; strong problem solving and debugging skills.
• Knowledge of Ethernet and PCIe Protocols, Serial/Parallel VIP verification, High‑speed SerDes.
• Excellent communication abilities to coordinate and articulate complex issues.

Responsibilities

• Develop verification infrastructure and test cases for ASICs in networking fabrics.
• Provide technical leadership in ASIC verification; run gate-level simulations, timing and power analysis.
• Deliver RTL coverage metrics and give actionable feedback to design engineers to broaden test coverage.
• Maintain QA standards and drive process improvements for efficiency and effectiveness.

Skills

ASIC verification

SystemVerilog/UVM

Constrained random

Functional coverage

Test plans

Gate/timing/power

Python/Perl/Tcl

Ethernet/PCIe

VIP verification

Strong communication

Education

ME/BE in Electrical Engineering or related

Tools

SystemVerilog

OVM/UVM

Job description

Key Responsibilities

• Specialized Verification Strategy: Develop verification infrastructure and test cases for ASICs in the area of network fabrics, leveraging your extensive experience in networking.
• Technical Expertise in ASIC Verification: Provide technical leadership in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications. Gate & Timing simulations: collaborate with the team to execute comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out.
• RTL Coverage Analysis: deliver detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to design engineers, focusing on identifying gaps and suggesting enhancements to elevate test effectiveness and broaden coverage scope.
• Quality Assurance and Process Optimization: Uphold the highest standards of verification quality. Initiate and implement process improvements for increased efficiency and effectiveness.

Qualifications

• ME/BE in Electrical Engineering, Computer Engineering, or related field.
• Experience: A MINIMUM of 8-15 years in ASIC verification in the area of data center networking.
• Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simulations, constrained random verification, and test‑plan documentation is required.
• Technical Skills: Python/Perl/Tcl experience, strong problem‑solving and debugging skill is a plus.
• Domain Knowledge: Prior experience with Ethernet and PCIe Protocols, Serial and Parallel VIP verification modes, and High‑speed SerDes is a strong plus.
• Communication Skills: Exceptional communication abilities, capable of effectively coordinating, and articulating complex technical issues in a clear manner.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.