Senior ASIC Verification Engineer: Data Center Networking

Eridu; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Eridu in San Francisco, CA seeks an experienced ASIC verification lead to design and implement verification strategies for data‑center networking ASICs. You will drive gate‑level simulations, coverage analysis, and verification planning, collaborating with design and software teams.

The role requires 8–15 years of hands‑on experience, a strong background in SystemVerilog/UVM, and expertise in Ethernet and PCIe protocols, with excellent communication to coordinate complex issues.

Qualifications

• ME/BE in Electrical Engineering, Computer Engineering, or related field.
• 8–15 years of ASIC verification experience in data center networking.
• Expertise in Hardware Verification and Hardware Verification Methodology (e.g., SystemVerilog, OVM/VMM/UVM).
• Experience with functional coverage, gate/timing/power simulations, constrained random verification, and test‑plan documentation.
• Python/Perl/Tcl experience; strong problem solving and debugging skills.
• Knowledge of Ethernet and PCIe Protocols, Serial/Parallel VIP verification, High‑speed SerDes.
• Excellent communication abilities to coordinate and articulate complex issues.

Responsibilities

• Develop verification infrastructure and test cases for ASICs in networking fabrics.
• Provide technical leadership in ASIC verification; run gate-level simulations, timing and power analysis.
• Deliver RTL coverage metrics and give actionable feedback to design engineers to broaden test coverage.
• Maintain QA standards and drive process improvements for efficiency and effectiveness.

Skills

ASIC verification

SystemVerilog/UVM

Constrained random

Functional coverage

Test plans

Gate/timing/power

Python/Perl/Tcl

Ethernet/PCIe

VIP verification

Strong communication

Education

ME/BE in Electrical Engineering or related

Tools

SystemVerilog

OVM/UVM

Job description

Eridu in San Francisco, CA seeks an experienced ASIC verification lead to design and implement verification strategies for data‑center networking ASICs. You will drive gate‑level simulations, coverage analysis, and verification planning, collaborating with design and software teams.

The role requires 8–15 years of hands‑on experience, a strong background in SystemVerilog/UVM, and expertise in Ethernet and PCIe protocols, with excellent communication to coordinate complex issues.