ASIC Design Verification Engineer

Yochana; United States; On-site; USD 120,000 - 160,000; Full time

Job summary

Yochana is seeking a senior ASIC verification engineer to take full ownership of block-level verification across 4–5 complex design blocks per project. You will build and maintain verification components, sequences, agents, scoreboards, and coverage models from scratch using SystemVerilog and UVM.

You will execute directed and constrained-random test scenarios, perform debugging, and drive closure of functional and code coverage.

Qualifications

• 6 to 10+ years of ASIC verification experience in complex digital designs.
• Expert-level SystemVerilog and UVM with testbench development from scratch.
• Hands-on verification with high-speed protocols such as Ethernet, PCIe, UCIe 2.0.
• Strong waveform analysis and debugging skills.
• Ability to work autonomously in a customer-facing environment.

Responsibilities

• Own block-level verification ownership for multiple blocks per project.
• Develop and maintain verification components, test sequences, agents, scoreboards, and coverage models from scratch.
• Execute directed and constrained-random test scenarios; drive coverage closure.
• Collaborate with customer teams and internal leads to align testbench with top-level.
• Perform debugging, triage, and regression analysis using simulators.

Skills

SystemVerilog

UVM

Testbench development

Digital design verification

Waveform analysis

Problem solving

Communication

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

• Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.


• Testbench & Component Development: Build and maintain verification components, test sequences, agents, scoreboards, and functional coverage models from scratch using SystemVerilog and UVM.


• Verification Execution: Execute directed and constrained-random test scenarios, perform rigorous test debugging, and drive functional and code coverage closure.


• Protocol Application: Apply deep working knowledge of advanced industry protocols such as UCIe (Universal Chiplet Interconnect Express) 2.0, PCIe, and Ethernet to verify complex architectural features.


• Collaboration: Interface smoothly with customer engineering teams and internal project leads, ensuring block-level verification aligns with the customer-owned top-level testbench infrastructure.


• Debugging & Triage: Perform in-depth waveform analysis, protocol debugging, root-cause analysis, and regression triage using industry-standard simulators.

Required Qualifications & Skills

• Experience: 6 to 10+ years of relevant hands-on ASIC verification experience in complex digital designs.


• Methodologies: Expert-level proficiency in SystemVerilog and UVM, with a proven history of developing testbenches, test sequences, agents, and other components from scratch.


• Protocol Knowledge: Hands-on verification experience with one or more high-speed protocols:

Ethernet (MAC/PCS/PMA layers)

• Domain Background: Proven track record working on complex networking silicon, Switches, NICs, or high-performance interconnect ASICs.


• Debugging Skills: Strong expertise in waveform analysis, protocol debugging, root-cause analysis, and regression triage using simulators (Synopsys VCS, Cadence Xcelium, or Mentor Questa).


• Soft Skills: Strong problem-solving abilities, solid communication skills, and the capability to work autonomously in a collaborative, customer-facing environment.