Principal DV Engineer

E-Space; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Job summary

E-Space is looking for a Digital Design Verification Engineer to join their team in Saratoga, California. The ideal candidate will verify custom ASICs for satellite and wireless telephony, leveraging over 10 years of design verification experience in the semiconductor industry. Expertise in Verilog, SystemVerilog, and UVM is essential. This full-time position offers a target base pay of $120,000 – $220,000 annually, with significant opportunities to innovate in satellite technology. Come make a difference at E-Space.

Qualifications

• Expert-level proficiency in Verilog and SystemVerilog.
• Proven experience building UVM verification environments from scratch.
• Deep understanding of verification methodologies and best practices.

Responsibilities

• Verify custom ASICs for satellite and wireless telephony.
• Write comprehensive test plans and maintain test suites.
• Debug complex RTL simulations and gate-level simulations.

Skills

Verilog

SystemVerilog

UVM

C/C++ coding

Scripting skills in Perl or Python

Bash scripting

Education

10+ years of design verification experience in the semiconductor industry

Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper‑scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space‑based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must; VHDL is valuable. We prioritize AI assistance to accelerate work.

Requirements

• HDL & Verification Methodology
• Expert‑level proficiency in Verilog and SystemVerilog
• Proven experience building UVM verification environments from scratch
• Deep understanding of verification methodologies and best practices

Programming & Scripting

• Proficient in C/C++ coding for verification purposes
• Strong scripting skills in Perl or Python
• Ability to write and maintain bash scripts for verification flows

Verification Planning & Execution

• Experience writing comprehensive test plans
• Experience writing and maintaining test suites
• Ability to debug complex RTL simulations
• Ability to debug gate‑level simulations with SDF back‑annotation
• Ability to assess whether SDF timing violations are benign or require attention

Leadership

• Proven track record leading code coverage closure
• Experience leading design verification efforts through chip tapeout

What you bring to this role

• 10+ years of design verification experience in the semiconductor industry

This is a full‑time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 – $220,000 annually. The total compensation package will be determined by various factors such as your relevant job‑related knowledge, skills, and experience.

We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in‑orbit activities. If that’s your experience, we’ll be immediately wowed.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.