Senior Design Verification Engineer

Viasat; Independence (OH); On-site; USD 141,500 - 224,000; Full time

Job summary

Viasat in Independence, Ohio, is seeking a Design Verification Engineer to develop cutting-edge communications technology. This role demands extensive experience in Design Verification and UVM testbench creation.

You'll work in a verification environment, ensuring quality via analysis of coverage metrics and debugging tests. Ideal candidates should have a Bachelor's degree in Electrical Engineering and 8+ years of relevant experience. The salary range is $141,500 - $224,000 annually.

Qualifications

• 8+ years Design Verification experience including UVM experience.
• Experience in UVM testbench creation and usage.
• Foundational knowledge of digital logic and timing considerations.

Responsibilities

• Architecting Design Verification environments for ASICs and FPGAs.
• Debugging failing tests, understanding UVM testbench and VHDL/Verilog code.

Skills

Design Verification

UVM Experience

Attention to detail

AI methodologies

Education

Bachelor's Degree in Electrical Engineering

Tools

Questa

Xcelium

VCS

Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

What you'll do

At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.

You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.

As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:

• Design verification planning including test plans
• Testbench development using SystemVerilog/UVM
• Hands‑on debug with the design team
• Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
• Managing regressions and compute resources
• Tool evaluation and license management
• Responsible for owning and driving technical issues to resolution

The day-to-day

• Architecting Design Verification environments for ASICs and FPGAs.

• Working with RTL, System and software engineers to determine appropriate coverage closure for chip designs.

• Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs.

• Maintaining and communicating program schedule and task tracking (Agile Jira based).

• Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers.

What you'll need

• 8+ years Design Verification experience including UVM experience
• Experience in UVM testbench creation and usage
• Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
• Experience with AI and agentic flow methodologies for design verification and chip development
• Foundational knowledge of digital logic and timing considerations
• Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
• Experience with industry standard simulators such as Questa, Xcelium and VCS
• Proven track record of work in UVM testbench development
• US citizenship
• Ability to travel up to 10%
• Must be able to obtain a secret clearance

What will help you on the job

• Strong written and verbal communication skills, ability to work with a geographically distributed team
• Object oriented programming experience
• Familiarity with designing and coding for testbench horizontal and vertical re-use
• Familiarity with AI coding agents for design verificaiton
• Ability to work independently, take initiative, and take ownership of tasks and results

#LI-AF1

Salary range

$141,500.00 - $224,000.00 / annually. For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $176,000.00- $264,000.00/ annually

At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.

EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.