Senior DV Engineer

E-Space; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Opportunity to really make a difference

Sustainability at our core

Fair and honest workplace

Innovative thinking is encouraged

Competitive salaries

Continuous learning and development

Health and wellness care options

Financial solutions for the future

Optional legal services (US only)

Paid holidays

Paid time off

Job summary

E-Space is looking for a Digital Design Verification Engineer in Saratoga, CA, to verify custom ASICs used in satellite and wireless telephony. The position requires proficiency in Verilog, SystemVerilog, and UVM, along with at least 4 years of relevant design verification experience in the semiconductor industry. E-Space offers a competitive salary with a target base pay between $120,000 and $220,000 annually, and benefits including health care options and paid time off.

Qualifications

• Proficiency in both Verilog and SystemVerilog is a must.
• Experience working with UVM architecture and methodology.
• Ability to write verification tests within an existing environment.
• 4+ years of experience in the semiconductor industry.

Responsibilities

• Verify custom ASICs for satellite and wireless telephony.
• Develop and maintain verification environments using Verilog, SystemVerilog, and UVM.

Skills

HDL & Verification Methodology

Proficiency in Verilog and SystemVerilog

Working knowledge of UVM architecture and methodology

Ability to write verification tests

Scripting in Perl, Python, or bash

4+ years of design verification experience

Job description

Join E‑Space as a Digital Design Verification Engineer to verify custom ASICs for satellite and wireless telephony. You will use Verilog, SystemVerilog, and UVM to develop and maintain verification environments.

Qualifications

• HDL & Verification Methodology.
• Proficiency in Verilog and SystemVerilog.
• Working knowledge of UVM architecture and methodology.
• Ability to write verification tests within an existing environment.
• Some experience scripting in Perl, Python, or bash.
• 4+ years of design verification experience in the semiconductor industry.

Compensation & Benefits

Full‑time, exempt position based out of our Saratoga office. Target base pay for this role is $120,000 – $220,000 annually. Total compensation will be determined by relevant job‑related knowledge, skills, and experience.

• Opportunity to really make a difference.
• Sustainability at our core.
• Fair and honest workplace.
• Innovative thinking is encouraged.
• Competitive salaries.
• Continuous learning and development.
• Health and wellness care options.
• Financial solutions for the future.
• Optional legal services (US only).
• Paid holidays.
• Paid time off.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.