Senior DV Engineer

Espace; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

An opportunity to make a difference

Sustainability at our core

Fair and honest workplace

Innovative thinking encouraged

Competitive salaries

Continuous learning and development

Health and wellness care options

Financial solutions for the future

Optional legal services (US only)

Paid holidays

Paid time off

Job summary

Espace is looking for a Digital Design Verification Engineer based in Saratoga, California. The role requires proficiency in Verilog and SystemVerilog, along with 4+ years of experience in the semiconductor industry. You will be responsible for verifying ASICs in satellite and wireless telephony.

The position offers a competitive salary in the range of $120,000-$220,000 per year and emphasizes continuous learning and wellness options.

Qualifications

• Proficiency in Verilog and SystemVerilog is essential.
• Working knowledge of UVM architecture and methodology needed.
• 4+ years of experience in design verification in semiconductor industry.

Responsibilities

• Verify custom ASICs for satellite and wireless telephony.
• Provide verification tests within an existing environment.
• Utilize AI assistance when possible.

Skills

Proficiency in Verilog and SystemVerilog

Working knowledge of UVM architecture and methodology

Experience writing verification tests

Scripting experience in Perl, Python, or bash

VHDL knowledge

4+ years of design verification experience

Job description

Position

Digital Design Verification Engineer - Satellite & Wireless Telephony

Responsibilities

Verify custom ASICs for satellite and wireless telephony. Provide verification tests within existing environment and utilize AI assistance when possible.

Qualifications

• Proficiency in Verilog and SystemVerilog
• Working knowledge of UVM architecture and methodology
• Experience writing verification tests within an existing environment
• Some scripting experience in Perl, Python, or bash
• VHDL knowledge is valuable
• 4+ years of design verification experience in the semiconductor industry

Employment Details

Full time, exempt. Location: Saratoga, CA. Target base pay: $120,000-$220,000 per year.

Policy

We do not provide employment sponsorship for candidates without work authorization for this location.

Benefits

• An opportunity to make a difference
• Sustainability at our core
• Fair and honest workplace
• Innovative thinking encouraged
• Competitive salaries
• Continuous learning and development
• Health and wellness care options
• Financial solutions for the future
• Optional legal services (US only)
• Paid holidays
• Paid time off