Senior SRAM Circuit Design Engineer – Low-Power SoC Architect

MaziCTools; United States; Remote; USD 167,000 - 296,000; Full time

Benefits offered by this job

Stock options

Relocation assistance

Education reimbursement

Job summary

Apple seeks an SRAM Circuit Design Engineer to join its Digital Custom Group. You will design and verify SRAM circuits, define architectures, and work with a team to push the boundaries of low-power, high-performance memory in flagship silicon like M1 and related products.

Role emphasizes RTL modeling, DFT, and collaboration with architecture and layout teams to ensure robust, scalable designs with strong silicon debug capabilities.

Qualifications

• Experience in SoC design cycles, SRAM/Register File for low power and high performance.
• Knowledge of cache design/architecture and memory hierarchy is a plus.
• Proficiency in RTL modeling and standard design tools.
• Solid understanding of nanometer device physics and leakage mechanisms.
• Ability to design experiments and analyze silicon data for debugging.
• Experience with ML algorithms and scripting is advantageous.

Responsibilities

• Design and implement custom digital circuits for SRAM design.
• Collaborate with logic/architecture teams to formulate design specs.
• Define architectures to optimize power, timing, area and yield.
• Perform schematic capture, simulations, margin verifications, and DFT modeling.
• Work with layout to create optimal GDS and verify against schematics.
• Back-end verification, IR/EM checks, and post-silicon support for productization.

Skills

SoC design experience

SRAM/Register File design

Cache design/architecture

RTL modeling

Industry-standard EDA tools

Device physics & leakage

Silicon debug/data analysis

ML algorithms & scripting

Education

BS in Electrical Engineering or related field

Tools

RTL design tools

Schematic capture tools

Job description

Apple seeks an SRAM Circuit Design Engineer to join its Digital Custom Group. You will design and verify SRAM circuits, define architectures, and work with a team to push the boundaries of low-power, high-performance memory in flagship silicon like M1 and related products.

Role emphasizes RTL modeling, DFT, and collaboration with architecture and layout teams to ensure robust, scalable designs with strong silicon debug capabilities.