TPU SoC ATE & Test Infra Engineer - NPI/HVM

Socket.dev; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

None

Job summary

Google is seeking an SoC Test Infrastructure Engineer to help shape the future of AI/ML hardware acceleration. You will drive post-silicon NPI and high-volume test strategies for our TPU and HPC products, developing and validating Automated Test Equipment programs and pre-silicon test solutions to ensure robust silicon from bring-up to mass production.

You will build automated tools and workflows to optimize the silicon testing life-cycle, collaborate with Architecture, Design, and Verification

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CS.
• 8 years of experience in test engineering.
• Experience with Python, Java, C#, or C/C++.
• Experience with Advantest or Teradyne platforms.

Responsibilities

• Collaborate with Architecture, Design, and Verification to develop product bring-up and test strategies.
• Verify test solutions on pre-silicon models and develop ATE modules, DC tests, and binning flows.
• Develop and validate ATE programs for new product integration in high-volume manufacturing.
• Build tools and methodologies to automate the testing life-cycle.
• Partner with upstream/downstream teams to enable automated testing solutions.

Skills

Python

Java

C/C++

Test engineering

Automated test tools

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (preferred)

Tools

Advantest

Teradyne

Job description

Google is seeking an SoC Test Infrastructure Engineer to help shape the future of AI/ML hardware acceleration. You will drive post-silicon NPI and high-volume test strategies for our TPU and HPC products, developing and validating Automated Test Equipment programs and pre-silicon test solutions to ensure robust silicon from bring-up to mass production.

You will build automated tools and workflows to optimize the silicon testing life-cycle, collaborate with Architecture, Design, and Verification