SoC DFT Engineer for AI/ML TPU Hardware

Google; United States; On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a mid-level SoC DFT Engineer specializing in design-for-test methodologies to shape the future of AI/ML hardware acceleration. You’ll verify complex digital designs, focusing on TPU architecture integration within AI/ML systems and collaborating with silicon engineering to improve yield and reduce test cost.

You will implement Scan, MBIST, JTAG, and iJTAG for IP blocks, define silicon test strategies, and contribute to next-generation TPU-related SoCs and test flows.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Responsibilities

• Develop and document DFT strategy, architecture, and test sequences, including hierarchical DFT, MBIST, ATPG, and I/JTAG.
• Complete all Test Design Rule Checks (TDRC) and fix Design changes to achieve high test quality.
• Develop diagnostic databases, software, and hardware for logic and memory fail debug.
• Design and implement system-level test strategy.
• Implement core DFT circuitry, including scan chains, DFT compression, Logic BIST, TAP controllers, and MBIST logic for IP blocks.

Skills

DFT verification

System-level test

Test methodology

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science (preferred)

Tools

ATE

MBIST

JTAG

SLT

Job description

Google is seeking a mid-level SoC DFT Engineer specializing in design-for-test methodologies to shape the future of AI/ML hardware acceleration. You’ll verify complex digital designs, focusing on TPU architecture integration within AI/ML systems and collaborating with silicon engineering to improve yield and reduce test cost.

You will implement Scan, MBIST, JTAG, and iJTAG for IP blocks, define silicon test strategies, and contribute to next-generation TPU-related SoCs and test flows.