TPU Silicon Design Engineer (RTL/Verilog, Power)

Google Inc.; Mountain View (CA); On-site; USD 118,000 - 197,000; Full time

Job summary

Google is seeking a hardware design engineer to advance custom silicon for our direct-to-consumer products in Mountain View, CA. You will help deliver high-performance, energy-efficient hardware with tight integration across the Google AI, Software, and Hardware teams.

The role emphasizes RTL design, digital logic, and collaboration with verification and silicon teams. A BS is required; a Master/PhD is preferred. In-person interviews are common; Mountain View, CA, USA is a preferred location.

Qualifications

• BS in EE/CE/CS or related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Responsibilities

• Use simulation/emulation/power analysis tools to ensure power and performance meet defined specifications.
• Develop, implement, and maintain design blocks or components/part of a hardware product, and integrate design blocks or components/parts to create product subsystems.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Take a leadership role on technical project teams and set technical direction.

Skills

Digital logic design

RTL design concepts

Verilog

SystemVerilog

Logic synthesis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

Google is seeking a hardware design engineer to advance custom silicon for our direct-to-consumer products in Mountain View, CA. You will help deliver high-performance, energy-efficient hardware with tight integration across the Google AI, Software, and Hardware teams.

The role emphasizes RTL design, digital logic, and collaboration with verification and silicon teams. A BS is required; a Master/PhD is preferred. In-person interviews are common; Mountain View, CA, USA is a preferred location.