TPU RTL Design Engineer for AI Accelerators

Socket.dev; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google in Sunnyvale seeks an RTL Design Engineer to shape the TPU microarchitecture and deliver high-quality SystemVerilog RTL for AI/ML accelerators. You will drive design decisions that balance performance, power, and area while collaborating with Verification and Physical Design to meet timing and manufacturability requirements.

You’ll own critical design deliverables, partner with DV and PD teams across the TPU ecosystem, and contribute to post-silicon validation and integration.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience in RTL design.
• Experience with digital design and microarchitecture design.
• Experience in design optimizing for performance, power, and area.

Responsibilities

• Define TPU microarchitecture and develop high-quality, performant, and power-efficient SystemVerilog RTL code for complex digital designs.
• Partner with Verification teams to develop test plans, debug RTL, and ensure functional correctness, alongside supporting post-silicon validation efforts.
• Collaborate closely with the Physical Design team to successfully meet stringent timing, area, power, and manufacturability requirements.
• Work seamlessly with internal Partner teams to support and drive critical design integration efforts across the ecosystem.

Skills

RTL design

digital design

microarchitecture design

performance optimization

power optimization

area optimization

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Python

Perl

Linting

CDC

RDC

LEC

ASIC synthesis flows

Job description

Google in Sunnyvale seeks an RTL Design Engineer to shape the TPU microarchitecture and deliver high-quality SystemVerilog RTL for AI/ML accelerators. You will drive design decisions that balance performance, power, and area while collaborating with Verification and Physical Design to meet timing and manufacturability requirements.

You’ll own critical design deliverables, partner with DV and PD teams across the TPU ecosystem, and contribute to post-silicon validation and integration.