Timing & Synthesis Engineer for Wireless SoCs

Apple; San Diego (CA); On-site; USD 139,500 - 258,100; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Employee stock programs

Educational reimbursement

Job summary

A leading technology company in San Diego is seeking a Timing Engineer to develop Wireless SoCs. In this role, you will collaborate with diverse teams to create and manage timing constraints essential for ASIC design. Candidates should hold a Bachelor's degree and possess at least 3 years of experience in the field. This position offers a competitive salary and comprehensive benefits including stock options and educational reimbursements.

Qualifications

• 3+ years of relevant industry experience.
• Strong knowledge of the ASIC design process.
• Expertise in static timing analysis.

Responsibilities

• Create and review timing constraints throughout the project.
• Execute low-power physical synthesis techniques.
• Collaborate with various teams for project success.

Skills

Timing constraint creation

Logic synthesis execution

Scripting languages (TCL, PERL, Python)

Education

Bachelor's degree

Tools

STA tools

Job description

A leading technology company in San Diego is seeking a Timing Engineer to develop Wireless SoCs. In this role, you will collaborate with diverse teams to create and manage timing constraints essential for ASIC design. Candidates should hold a Bachelor's degree and possess at least 3 years of experience in the field. This position offers a competitive salary and comprehensive benefits including stock options and educational reimbursements.